104 lines · yaml
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)2%YAML 1.23---4$id: http://devicetree.org/schemas/phy/fsl,imx8mq-usb-phy.yaml#5$schema: http://devicetree.org/meta-schemas/core.yaml#6 7title: Freescale i.MX8MQ USB3 PHY8 9maintainers:10 - Li Jun <jun.li@nxp.com>11 12properties:13 compatible:14 enum:15 - fsl,imx8mq-usb-phy16 - fsl,imx8mp-usb-phy17 18 reg:19 maxItems: 120 21 "#phy-cells":22 const: 023 24 clocks:25 maxItems: 126 27 clock-names:28 items:29 - const: phy30 31 power-domains:32 maxItems: 133 34 vbus-supply:35 description:36 A phandle to the regulator for USB VBUS.37 38 fsl,phy-tx-vref-tune-percent:39 description:40 Tunes the HS DC level relative to the nominal level41 minimum: 9442 maximum: 12443 44 fsl,phy-tx-rise-tune-percent:45 description:46 Adjusts the rise/fall time duration of the HS waveform relative to47 its nominal value48 minimum: 9749 maximum: 10350 51 fsl,phy-tx-preemp-amp-tune-microamp:52 description:53 Adjust amount of current sourced to DPn and DMn after a J-to-K54 or K-to-J transition. Default is 0 (disabled).55 minimum: 056 maximum: 180057 58 fsl,phy-tx-vboost-level-microvolt:59 description:60 Adjust the boosted transmit launch pk-pk differential amplitude61 minimum: 88062 maximum: 112063 64 fsl,phy-comp-dis-tune-percent:65 description:66 Adjust the voltage level used to detect a disconnect event at the host67 relative to the nominal value68 minimum: 9169 maximum: 11570 71 fsl,phy-pcs-tx-deemph-3p5db-attenuation-db:72 description:73 Adjust TX de-emphasis attenuation in dB at nominal74 3.5dB point as per USB specification75 $ref: /schemas/types.yaml#/definitions/uint3276 minimum: 077 maximum: 3678 79 fsl,phy-pcs-tx-swing-full-percent:80 description:81 Scaling of the voltage defined by fsl,phy-tx-vboost-level-microvolt82 minimum: 083 maximum: 10084 85required:86 - compatible87 - reg88 - "#phy-cells"89 - clocks90 - clock-names91 92additionalProperties: false93 94examples:95 - |96 #include <dt-bindings/clock/imx8mq-clock.h>97 usb3_phy0: phy@381f0040 {98 compatible = "fsl,imx8mq-usb-phy";99 reg = <0x381f0040 0x40>;100 clocks = <&clk IMX8MQ_CLK_USB1_PHY_ROOT>;101 clock-names = "phy";102 #phy-cells = <0>;103 };104