57 lines · yaml
1# SPDX-License-Identifier: GPL-2.02%YAML 1.23---4$id: http://devicetree.org/schemas/phy/hisilicon,hi3798cv200-combphy.yaml#5$schema: http://devicetree.org/meta-schemas/core.yaml#6 7title: HiSilicon STB PCIE/SATA/USB3 PHY8 9maintainers:10 - Shawn Guo <shawn.guo@linaro.org>11 12properties:13 compatible:14 const: hisilicon,hi3798cv200-combphy15 16 reg:17 maxItems: 118 19 '#phy-cells':20 description: The cell contains the PHY mode21 const: 122 23 clocks:24 maxItems: 125 26 resets:27 maxItems: 128 29 hisilicon,fixed-mode:30 description: If the phy device doesn't support mode select but a fixed mode31 setting, the property should be present to specify the particular mode.32 $ref: /schemas/types.yaml#/definitions/uint3233 enum: [ 1, 2, 4] # SATA, PCIE, USB334 35 hisilicon,mode-select-bits:36 description: If the phy device support mode select, this property should be37 present to specify the register bits in peripheral controller.38 items:39 - description: register_offset40 - description: bit shift41 - description: bit mask42 43required:44 - compatible45 - reg46 - '#phy-cells'47 - clocks48 - resets49 50oneOf:51 - required: ['hisilicon,fixed-mode']52 - required: ['hisilicon,mode-select-bits']53 54additionalProperties: false55 56...57