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1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)2%YAML 1.23---4$id: http://devicetree.org/schemas/phy/intel,combo-phy.yaml#5$schema: http://devicetree.org/meta-schemas/core.yaml#6 7title: Intel ComboPhy Subsystem8 9maintainers:10 - Dilip Kota <eswara.kota@linux.intel.com>11 12description: |13 Intel Combophy subsystem supports PHYs for PCIe, EMAC and SATA14 controllers. A single Combophy provides two PHY instances.15 16properties:17 $nodename:18 pattern: "combophy(@.*|-([0-9]|[1-9][0-9]+))?$"19 20 compatible:21 items:22 - const: intel,combophy-lgm23 - const: intel,combo-phy24 25 clocks:26 maxItems: 127 28 reg:29 items:30 - description: ComboPhy core registers31 - description: PCIe app core control registers32 33 reg-names:34 items:35 - const: core36 - const: app37 38 resets:39 maxItems: 440 41 reset-names:42 items:43 - const: phy44 - const: core45 - const: iphy046 - const: iphy147 48 intel,syscfg:49 $ref: /schemas/types.yaml#/definitions/phandle-array50 items:51 - items:52 - description: phandle to Chip configuration registers53 - description: ComboPhy instance id54 description: Chip configuration registers handle and ComboPhy instance id55 56 intel,hsio:57 $ref: /schemas/types.yaml#/definitions/phandle-array58 items:59 - items:60 - description: phandle to HSIO registers61 - description: ComboPhy instance id62 description: HSIO registers handle and ComboPhy instance id on NOC63 64 intel,aggregation:65 type: boolean66 description: |67 Specify the flag to configure ComboPHY in dual lane mode.68 69 intel,phy-mode:70 $ref: /schemas/types.yaml#/definitions/uint3271 description: |72 Mode of the two phys in ComboPhy.73 See dt-bindings/phy/phy.h for values.74 75 "#phy-cells":76 const: 177 78required:79 - compatible80 - clocks81 - reg82 - reg-names83 - intel,syscfg84 - intel,hsio85 - intel,phy-mode86 - "#phy-cells"87 88additionalProperties: false89 90examples:91 - |92 #include <dt-bindings/phy/phy.h>93 combophy@d0a00000 {94 compatible = "intel,combophy-lgm", "intel,combo-phy";95 clocks = <&cgu0 1>;96 #phy-cells = <1>;97 reg = <0xd0a00000 0x40000>,98 <0xd0a40000 0x1000>;99 reg-names = "core", "app";100 resets = <&rcu0 0x50 6>,101 <&rcu0 0x50 17>,102 <&rcu0 0x50 23>,103 <&rcu0 0x50 24>;104 reset-names = "phy", "core", "iphy0", "iphy1";105 intel,syscfg = <&sysconf 0>;106 intel,hsio = <&hsiol 0>;107 intel,phy-mode = <PHY_TYPE_PCIE>;108 intel,aggregation;109 };110