96 lines · yaml
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)2%YAML 1.23---4$id: http://devicetree.org/schemas/phy/lantiq,vrx200-pcie-phy.yaml#5$schema: http://devicetree.org/meta-schemas/core.yaml#6 7title: Lantiq VRX200 and ARX300 PCIe PHY8 9maintainers:10 - Martin Blumenstingl <martin.blumenstingl@googlemail.com>11 12properties:13 "#phy-cells":14 const: 115 description: selects the PHY mode as defined in <dt-bindings/phy/phy-lantiq-vrx200-pcie.h>16 17 compatible:18 enum:19 - lantiq,vrx200-pcie-phy20 - lantiq,arx300-pcie-phy21 22 reg:23 maxItems: 124 25 clocks:26 items:27 - description: PHY module clock28 - description: PDI register clock29 30 clock-names:31 items:32 - const: phy33 - const: pdi34 35 resets:36 items:37 - description: exclusive PHY reset line38 - description: shared reset line between the PCIe PHY and PCIe controller39 40 reset-names:41 items:42 - const: phy43 - const: pcie44 45 lantiq,rcu:46 $ref: /schemas/types.yaml#/definitions/phandle47 description: phandle to the RCU syscon48 49 lantiq,rcu-endian-offset:50 $ref: /schemas/types.yaml#/definitions/uint3251 description: the offset of the endian registers for this PHY instance in the RCU syscon52 53 lantiq,rcu-big-endian-mask:54 $ref: /schemas/types.yaml#/definitions/uint3255 description: the mask to set the PDI (PHY) registers for this PHY instance to big endian56 57 big-endian:58 description: Configures the PDI (PHY) registers in big-endian mode59 type: boolean60 61 little-endian:62 description: Configures the PDI (PHY) registers in big-endian mode63 type: boolean64 65required:66 - "#phy-cells"67 - compatible68 - reg69 - clocks70 - clock-names71 - resets72 - reset-names73 - lantiq,rcu74 - lantiq,rcu-endian-offset75 - lantiq,rcu-big-endian-mask76 77additionalProperties: false78 79examples:80 - |81 pcie0_phy: phy@106800 {82 compatible = "lantiq,vrx200-pcie-phy";83 reg = <0x106800 0x100>;84 lantiq,rcu = <&rcu0>;85 lantiq,rcu-endian-offset = <0x4c>;86 lantiq,rcu-big-endian-mask = <0x80>; /* bit 7 */87 big-endian;88 clocks = <&pmu 32>, <&pmu 36>;89 clock-names = "phy", "pdi";90 resets = <&reset0 12 24>, <&reset0 22 22>;91 reset-names = "phy", "pcie";92 #phy-cells = <1>;93 };94 95...96