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1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)2# Copyright (c) 2020 MediaTek3%YAML 1.24---5$id: http://devicetree.org/schemas/phy/mediatek,tphy.yaml#6$schema: http://devicetree.org/meta-schemas/core.yaml#7 8title: MediaTek T-PHY Controller9 10maintainers:11 - Chunfeng Yun <chunfeng.yun@mediatek.com>12 13description: |14 The T-PHY controller supports physical layer functionality for a number of15 controllers on MediaTek SoCs, includes USB2.0, USB3.0, PCIe and SATA.16 17 Layout differences of banks between T-PHY V1 (mt8173/mt2701) and18 T-PHY V2 (mt2712) / V3 (mt8195) when works on USB mode:19 -----------------------------------20 Version 1:21 port offset bank22 shared 0x0000 SPLLC23 0x0100 FMREG24 u2 port0 0x0800 U2PHY_COM25 u3 port0 0x0900 U3PHYD26 0x0a00 U3PHYD_BANK227 0x0b00 U3PHYA28 0x0c00 U3PHYA_DA29 u2 port1 0x1000 U2PHY_COM30 u3 port1 0x1100 U3PHYD31 0x1200 U3PHYD_BANK232 0x1300 U3PHYA33 0x1400 U3PHYA_DA34 u2 port2 0x1800 U2PHY_COM35 ...36 37 Version 2/3:38 port offset bank39 u2 port0 0x0000 MISC40 0x0100 FMREG41 0x0300 U2PHY_COM42 u3 port0 0x0700 SPLLC43 0x0800 CHIP44 0x0900 U3PHYD45 0x0a00 U3PHYD_BANK246 0x0b00 U3PHYA47 0x0c00 U3PHYA_DA48 u2 port1 0x1000 MISC49 0x1100 FMREG50 0x1300 U2PHY_COM51 u3 port1 0x1700 SPLLC52 0x1800 CHIP53 0x1900 U3PHYD54 0x1a00 U3PHYD_BANK255 0x1b00 U3PHYA56 0x1c00 U3PHYA_DA57 u2 port2 0x2000 MISC58 ...59 60 SPLLC shared by u3 ports and FMREG shared by u2 ports on V1 are put back61 into each port; a new bank MISC for u2 ports and CHIP for u3 ports are62 added on V2; the FMREG bank for slew rate calibration is not used anymore63 and reserved on V3;64 65properties:66 $nodename:67 pattern: "^t-phy(@[0-9a-f]+)?$"68 69 compatible:70 oneOf:71 - items:72 - enum:73 - mediatek,mt2701-tphy74 - mediatek,mt7623-tphy75 - mediatek,mt7622-tphy76 - mediatek,mt8516-tphy77 - const: mediatek,generic-tphy-v178 - items:79 - enum:80 - mediatek,mt2712-tphy81 - mediatek,mt7629-tphy82 - mediatek,mt7986-tphy83 - mediatek,mt8183-tphy84 - mediatek,mt8186-tphy85 - mediatek,mt8192-tphy86 - mediatek,mt8365-tphy87 - const: mediatek,generic-tphy-v288 - items:89 - enum:90 - mediatek,mt8188-tphy91 - mediatek,mt8195-tphy92 - const: mediatek,generic-tphy-v393 - const: mediatek,mt2701-u3phy94 deprecated: true95 - const: mediatek,mt2712-u3phy96 deprecated: true97 - const: mediatek,mt8173-u3phy98 99 reg:100 description:101 Register shared by multiple ports, exclude port's private register.102 It is needed for T-PHY V1, such as mt2701 and mt8173, but not for103 T-PHY V2/V3, such as mt2712.104 maxItems: 1105 106 "#address-cells":107 enum: [1, 2]108 109 "#size-cells":110 enum: [1, 2]111 112 # Used with non-empty value if optional 'reg' is not provided.113 # The format of the value is an arbitrary number of triplets of114 # (child-bus-address, parent-bus-address, length).115 ranges: true116 117 mediatek,src-ref-clk-mhz:118 description:119 Frequency of reference clock for slew rate calibrate120 default: 26121 122 mediatek,src-coef:123 description:124 Coefficient for slew rate calibrate, depends on SoC process125 $ref: /schemas/types.yaml#/definitions/uint32126 default: 28127 128# Required child node:129patternProperties:130 "^(usb|pcie|sata)-phy@[0-9a-f]+$":131 type: object132 description:133 A sub-node is required for each port the controller provides.134 Address range information including the usual 'reg' property135 is used inside these nodes to describe the controller's topology.136 137 properties:138 reg:139 maxItems: 1140 141 clocks:142 minItems: 1143 items:144 - description: Reference clock, (HS is 48Mhz, SS/P is 24~27Mhz)145 - description: Reference clock of analog phy146 description:147 Uses both clocks if the clock of analog and digital phys are148 separated, otherwise uses "ref" clock only if needed.149 150 clock-names:151 minItems: 1152 items:153 - const: ref154 - const: da_ref155 156 "#phy-cells":157 const: 1158 description: |159 The cells contain the following arguments.160 161 - description: The PHY type162 enum:163 - PHY_TYPE_USB2164 - PHY_TYPE_USB3165 - PHY_TYPE_PCIE166 - PHY_TYPE_SATA167 - PHY_TYPE_SGMII168 169 nvmem-cells:170 items:171 - description: internal R efuse for U2 PHY or U3/PCIe PHY172 - description: rx_imp_sel efuse for U3/PCIe PHY173 - description: tx_imp_sel efuse for U3/PCIe PHY174 description: |175 Phandles to nvmem cell that contains the efuse data;176 Available only for U2 PHY or U3/PCIe PHY of version 2/3, these177 three items should be provided at the same time for U3/PCIe PHY,178 when use software to load efuse;179 If unspecified, will use hardware auto-load efuse.180 181 nvmem-cell-names:182 items:183 - const: intr184 - const: rx_imp185 - const: tx_imp186 187 # The following optional vendor properties are only for debug or HQA test188 mediatek,eye-src:189 description:190 The value of slew rate calibrate (U2 phy)191 $ref: /schemas/types.yaml#/definitions/uint32192 minimum: 1193 maximum: 7194 195 mediatek,eye-vrt:196 description:197 The selection of VRT reference voltage (U2 phy)198 $ref: /schemas/types.yaml#/definitions/uint32199 minimum: 1200 maximum: 7201 202 mediatek,eye-term:203 description:204 The selection of HS_TX TERM reference voltage (U2 phy)205 $ref: /schemas/types.yaml#/definitions/uint32206 minimum: 1207 maximum: 7208 209 mediatek,intr:210 description:211 The selection of internal resistor (U2 phy)212 $ref: /schemas/types.yaml#/definitions/uint32213 minimum: 1214 maximum: 31215 216 mediatek,discth:217 description:218 The selection of disconnect threshold (U2 phy)219 $ref: /schemas/types.yaml#/definitions/uint32220 minimum: 1221 maximum: 15222 223 mediatek,pre-emphasis:224 description:225 The level of pre-emphasis which used to widen the eye opening and226 boost eye swing, the unit step is about 4.16% increment; e.g. the227 level 1 means amplitude increases about 4.16%, the level 2 is about228 8.3% etc. (U2 phy)229 $ref: /schemas/types.yaml#/definitions/uint32230 minimum: 1231 maximum: 3232 233 mediatek,bc12:234 description:235 Specify the flag to enable BC1.2 if support it236 type: boolean237 238 mediatek,force-mode:239 description:240 The force mode is used to manually switch the shared phy mode between241 USB3 and PCIe, when USB3 phy type is selected by the consumer, and242 force-mode is set, will cause phy's power and pipe toggled and force243 phy as USB3 mode which switched from default PCIe mode. But prefer to244 use the property "mediatek,syscon-type" for newer SoCs that support it.245 type: boolean246 247 mediatek,syscon-type:248 $ref: /schemas/types.yaml#/definitions/phandle-array249 maxItems: 1250 description:251 A phandle to syscon used to access the register of type switch,252 the field should always be 3 cells long.253 items:254 items:255 - description:256 The first cell represents a phandle to syscon257 - description:258 The second cell represents the register offset259 - description:260 The third cell represents the index of config segment261 enum: [0, 1, 2, 3]262 263 required:264 - reg265 - "#phy-cells"266 267 additionalProperties: false268 269required:270 - compatible271 - "#address-cells"272 - "#size-cells"273 - ranges274 275additionalProperties: false276 277examples:278 - |279 #include <dt-bindings/clock/mt8173-clk.h>280 #include <dt-bindings/interrupt-controller/arm-gic.h>281 #include <dt-bindings/interrupt-controller/irq.h>282 #include <dt-bindings/phy/phy.h>283 usb@11271000 {284 compatible = "mediatek,mt8173-mtu3", "mediatek,mtu3";285 reg = <0x11271000 0x3000>, <0x11280700 0x0100>;286 reg-names = "mac", "ippc";287 phys = <&u2port0 PHY_TYPE_USB2>,288 <&u3port0 PHY_TYPE_USB3>,289 <&u2port1 PHY_TYPE_USB2>;290 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_LOW>;291 clocks = <&topckgen CLK_TOP_USB30_SEL>;292 clock-names = "sys_ck";293 };294 295 t-phy@11290000 {296 compatible = "mediatek,mt8173-u3phy";297 reg = <0x11290000 0x800>;298 #address-cells = <1>;299 #size-cells = <1>;300 ranges;301 302 u2port0: usb-phy@11290800 {303 reg = <0x11290800 0x100>;304 clocks = <&apmixedsys CLK_APMIXED_REF2USB_TX>, <&clk48m>;305 clock-names = "ref", "da_ref";306 #phy-cells = <1>;307 };308 309 u3port0: usb-phy@11290900 {310 reg = <0x11290900 0x700>;311 clocks = <&clk26m>;312 clock-names = "ref";313 #phy-cells = <1>;314 };315 316 u2port1: usb-phy@11291000 {317 reg = <0x11291000 0x100>;318 #phy-cells = <1>;319 };320 };321 322...323