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1# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause2%YAML 1.23---4$id: http://devicetree.org/schemas/phy/microchip,lan966x-serdes.yaml#5$schema: http://devicetree.org/meta-schemas/core.yaml#6 7title: Microchip Lan966x Serdes controller8 9maintainers:10 - Horatiu Vultur <horatiu.vultur@microchip.com>11 12description: |13 Lan966x has 7 interfaces, consisting of 2 copper transceivers(CU),14 3 SERDES6G and 2 RGMII interfaces. Two of the SERDES6G support QSGMII.15 Also it has 8 logical Ethernet ports which can be connected to these16 interfaces. The Serdes controller will allow to configure these interfaces17 and allows to "mux" the interfaces to different ports.18 19 For simple selection of the interface that is used with a port, the20 following macros are defined CU(X), SERDES6G(X), RGMII(X). Where X is a21 number that represents the index of that interface type. For example22 CU(1) means use interface copper transceivers 1. SERDES6G(2) means use23 interface SerDes 2.24 25properties:26 $nodename:27 pattern: "^serdes@[0-9a-f]+$"28 29 compatible:30 const: microchip,lan966x-serdes31 32 reg:33 items:34 - description: HSIO registers35 - description: HW_STAT register36 37 '#phy-cells':38 const: 239 description: |40 - Input port to use for a given macro.41 - The macro to be used. The macros are defined in42 dt-bindings/phy/phy-lan966x-serdes.43 44required:45 - compatible46 - reg47 - '#phy-cells'48 49additionalProperties: false50 51examples:52 - |53 serdes: serdes@e2004010 {54 compatible = "microchip,lan966x-serdes";55 reg = <0xe202c000 0x9c>, <0xe2004010 0x4>;56 #phy-cells = <2>;57 };58 59...60