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1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)2%YAML 1.23---4$id: http://devicetree.org/schemas/phy/mixel,mipi-dsi-phy.yaml#5$schema: http://devicetree.org/meta-schemas/core.yaml#6 7title: Mixel DSI PHY for i.MX88 9maintainers:10 - Guido Günther <agx@sigxcpu.org>11 12description: |13 The Mixel MIPI-DSI PHY IP block is e.g. found on i.MX8 platforms (along the14 MIPI-DSI IP from Northwest Logic). It represents the physical layer for the15 electrical signals for DSI.16 17 The Mixel PHY IP block found on i.MX8qxp is a combo PHY that can work18 in either MIPI-DSI PHY mode or LVDS PHY mode.19 20properties:21 compatible:22 enum:23 - fsl,imx8mq-mipi-dphy24 - fsl,imx8qxp-mipi-dphy25 26 reg:27 maxItems: 128 29 clocks:30 maxItems: 131 32 clock-names:33 const: phy_ref34 35 "#phy-cells":36 const: 037 38 fsl,syscon:39 $ref: /schemas/types.yaml#/definitions/phandle40 description: |41 A phandle which points to Control and Status Registers(CSR) module.42 43 power-domains:44 maxItems: 145 46required:47 - compatible48 - reg49 - clocks50 - clock-names51 - "#phy-cells"52 - power-domains53 54allOf:55 - if:56 properties:57 compatible:58 contains:59 const: fsl,imx8mq-mipi-dphy60 then:61 properties:62 fsl,syscon: false63 64 required:65 - assigned-clocks66 - assigned-clock-parents67 - assigned-clock-rates68 69 - if:70 properties:71 compatible:72 contains:73 const: fsl,imx8qxp-mipi-dphy74 then:75 properties:76 assigned-clocks: false77 assigned-clock-parents: false78 assigned-clock-rates: false79 80 required:81 - fsl,syscon82 83additionalProperties: false84 85examples:86 - |87 #include <dt-bindings/clock/imx8mq-clock.h>88 dphy: dphy@30a0030 {89 compatible = "fsl,imx8mq-mipi-dphy";90 reg = <0x30a00300 0x100>;91 clocks = <&clk IMX8MQ_CLK_DSI_PHY_REF>;92 clock-names = "phy_ref";93 assigned-clocks = <&clk IMX8MQ_CLK_DSI_PHY_REF>;94 assigned-clock-parents = <&clk IMX8MQ_VIDEO_PLL1_OUT>;95 assigned-clock-rates = <24000000>;96 #phy-cells = <0>;97 power-domains = <&pgc_mipi>;98 };99