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1# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause2%YAML 1.23---4$id: http://devicetree.org/schemas/phy/nvidia,tegra124-xusb-padctl.yaml#5$schema: http://devicetree.org/meta-schemas/core.yaml#6 7title: NVIDIA Tegra124 XUSB pad controller8 9maintainers:10 - Thierry Reding <thierry.reding@gmail.com>11 - Jon Hunter <jonathanh@nvidia.com>12 13description: |14 The Tegra XUSB pad controller manages a set of I/O lanes (with differential15 signals) which connect directly to pins/pads on the SoC package. Each lane16 is controlled by a HW block referred to as a "pad" in the Tegra hardware17 documentation. Each such "pad" may control either one or multiple lanes,18 and thus contains any logic common to all its lanes. Each lane can be19 separately configured and powered up.20 21 Some of the lanes are high-speed lanes, which can be used for PCIe, SATA or22 super-speed USB. Other lanes are for various types of low-speed, full-speed23 or high-speed USB (such as UTMI, ULPI and HSIC). The XUSB pad controller24 contains a software-configurable mux that sits between the I/O controller25 ports (e.g. PCIe) and the lanes.26 27 In addition to per-lane configuration, USB 3.0 ports may require additional28 settings on a per-board basis.29 30 Pads will be represented as children of the top-level XUSB pad controller31 device tree node. Each lane exposed by the pad will be represented by its32 own subnode and can be referenced by users of the lane using the standard33 PHY bindings, as described by the phy-bindings.txt file in this directory.34 35 The Tegra hardware documentation refers to the connection between the XUSB36 pad controller and the XUSB controller as "ports". This is confusing since37 "port" is typically used to denote the physical USB receptacle. The device38 tree binding in this document uses the term "port" to refer to the logical39 abstraction of the signals that are routed to a USB receptacle (i.e. a PHY40 for the USB signal, the VBUS power supply, the USB 2.0 companion port for41 USB 3.0 receptacles, ...).42 43properties:44 compatible:45 oneOf:46 - enum:47 - nvidia,tegra124-xusb-padctl48 49 - items:50 - const: nvidia,tegra132-xusb-padctl51 - const: nvidia,tegra124-xusb-padctl52 53 reg:54 maxItems: 155 56 interrupts:57 items:58 - description: XUSB pad controller interrupt59 60 resets:61 items:62 - description: pad controller reset63 64 reset-names:65 items:66 - const: padctl67 68 avdd-pll-utmip-supply:69 description: UTMI PLL power supply. Must supply 1.8 V.70 71 avdd-pll-erefe-supply:72 description: PLLE reference PLL power supply. Must supply 1.05 V.73 74 avdd-pex-pll-supply:75 description: PCIe/USB3 PLL power supply. Must supply 1.05 V.76 77 hvdd-pex-pll-e-supply:78 description: High-voltage PLLE power supply. Must supply 3.3 V.79 80 pads:81 description: A required child node named "pads" contains a list of82 subnodes, one for each of the pads exposed by the XUSB pad controller.83 Each pad may need additional resources that can be referenced in its84 pad node.85 86 The "status" property is used to enable or disable the use of a pad.87 If set to "disabled", the pad will not be used on the given board. In88 order to use the pad and any of its lanes, this property must be set89 to "okay" or be absent.90 type: object91 additionalProperties: false92 properties:93 usb2:94 type: object95 additionalProperties: false96 properties:97 clocks:98 items:99 - description: USB2 tracking clock100 101 clock-names:102 items:103 - const: trk104 105 lanes:106 type: object107 additionalProperties: false108 properties:109 usb2-0:110 type: object111 additionalProperties: false112 properties:113 "#phy-cells":114 const: 0115 116 nvidia,function:117 description: Function selection for this lane.118 $ref: /schemas/types.yaml#/definitions/string119 enum: [ snps, xusb, uart ]120 121 usb2-1:122 type: object123 additionalProperties: false124 properties:125 "#phy-cells":126 const: 0127 128 nvidia,function:129 description: Function selection for this lane.130 $ref: /schemas/types.yaml#/definitions/string131 enum: [ snps, xusb, uart ]132 133 usb2-2:134 type: object135 additionalProperties: false136 properties:137 "#phy-cells":138 const: 0139 140 nvidia,function:141 description: Function selection for this lane.142 $ref: /schemas/types.yaml#/definitions/string143 enum: [ snps, xusb, uart ]144 145 ulpi:146 type: object147 additionalProperties: false148 properties:149 lanes:150 type: object151 additionalProperties: false152 properties:153 ulpi-0:154 type: object155 additionalProperties: false156 properties:157 "#phy-cells":158 const: 0159 160 nvidia,function:161 description: Function selection for this lane.162 $ref: /schemas/types.yaml#/definitions/string163 enum: [ snps, xusb ]164 165 hsic:166 type: object167 additionalProperties: false168 properties:169 clocks:170 items:171 - description: HSIC tracking clock172 173 clock-names:174 items:175 - const: trk176 177 lanes:178 type: object179 additionalProperties: false180 properties:181 hsic-0:182 type: object183 additionalProperties: false184 properties:185 "#phy-cells":186 const: 0187 188 nvidia,function:189 description: Function selection for this lane.190 $ref: /schemas/types.yaml#/definitions/string191 enum: [ snps, xusb ]192 193 hsic-1:194 type: object195 additionalProperties: false196 properties:197 "#phy-cells":198 const: 0199 200 nvidia,function:201 description: Function selection for this lane.202 $ref: /schemas/types.yaml#/definitions/string203 enum: [ snps, xusb ]204 205 pcie:206 type: object207 additionalProperties: false208 properties:209 clocks:210 items:211 - description: PLLE clock212 213 clock-names:214 items:215 - const: pll216 217 resets:218 items:219 - description: reset for the PCIe UPHY block220 221 reset-names:222 items:223 - const: phy224 225 lanes:226 type: object227 additionalProperties: false228 properties:229 pcie-0:230 type: object231 additionalProperties: false232 properties:233 "#phy-cells":234 const: 0235 236 nvidia,function:237 description: Function selection for this lane.238 $ref: /schemas/types.yaml#/definitions/string239 enum: [ pcie, usb3-ss ]240 241 pcie-1:242 type: object243 additionalProperties: false244 properties:245 "#phy-cells":246 const: 0247 248 nvidia,function:249 description: Function selection for this lane.250 $ref: /schemas/types.yaml#/definitions/string251 enum: [ pcie, usb3-ss ]252 253 pcie-2:254 type: object255 additionalProperties: false256 properties:257 "#phy-cells":258 const: 0259 260 nvidia,function:261 description: Function selection for this lane.262 $ref: /schemas/types.yaml#/definitions/string263 enum: [ pcie, usb3-ss ]264 265 pcie-3:266 type: object267 additionalProperties: false268 properties:269 "#phy-cells":270 const: 0271 272 nvidia,function:273 description: Function selection for this lane.274 $ref: /schemas/types.yaml#/definitions/string275 enum: [ pcie, usb3-ss ]276 277 pcie-4:278 type: object279 additionalProperties: false280 properties:281 "#phy-cells":282 const: 0283 284 nvidia,function:285 description: Function selection for this lane.286 $ref: /schemas/types.yaml#/definitions/string287 enum: [ pcie, usb3-ss ]288 289 sata:290 type: object291 additionalProperties: false292 properties:293 resets:294 items:295 - description: reset for the SATA UPHY block296 297 reset-names:298 items:299 - const: phy300 301 lanes:302 type: object303 additionalProperties: false304 properties:305 sata-0:306 type: object307 additionalProperties: false308 properties:309 "#phy-cells":310 const: 0311 312 nvidia,function:313 description: Function selection for this lane.314 $ref: /schemas/types.yaml#/definitions/string315 enum: [ sata, usb3-ss ]316 317 ports:318 description: A required child node named "ports" contains a list of319 subnodes, one for each of the ports exposed by the XUSB pad controller.320 Each port may need additional resources that can be referenced in its321 port node.322 323 The "status" property is used to enable or disable the use of a port.324 If set to "disabled", the port will not be used on the given board. In325 order to use the port, this property must be set to "okay".326 type: object327 additionalProperties: false328 properties:329 usb2-0:330 type: object331 additionalProperties: false332 properties:333 # no need to further describe this because the connector will334 # match on gpio-usb-b-connector or usb-b-connector and cause335 # that binding to be selected for the subnode336 connector:337 type: object338 339 mode:340 description: A string that determines the mode in which to341 run the port.342 $ref: /schemas/types.yaml#/definitions/string343 enum: [ host, peripheral, otg ]344 345 nvidia,internal:346 description: A boolean property whose presence determines347 that a port is internal. In the absence of this property348 the port is considered to be external.349 $ref: /schemas/types.yaml#/definitions/flag350 351 usb-role-switch:352 description: |353 A boolean property whole presence indicates that the port354 supports OTG or peripheral mode. If present, the port355 supports switching between USB host and peripheral roles.356 A connector must be added as a subnode in that case.357 358 See ../connector/usb-connector.yaml.359 360 vbus-supply:361 description: A phandle to the regulator supplying the VBUS362 voltage.363 364 usb2-1:365 type: object366 additionalProperties: false367 properties:368 # no need to further describe this because the connector will369 # match on gpio-usb-b-connector or usb-b-connector and cause370 # that binding to be selected for the subnode371 connector:372 type: object373 374 mode:375 description: A string that determines the mode in which to376 run the port.377 $ref: /schemas/types.yaml#/definitions/string378 enum: [ host, peripheral, otg ]379 380 nvidia,internal:381 description: A boolean property whose presence determines382 that a port is internal. In the absence of this property383 the port is considered to be external.384 $ref: /schemas/types.yaml#/definitions/flag385 386 usb-role-switch:387 description: |388 A boolean property whole presence indicates that the port389 supports OTG or peripheral mode. If present, the port390 supports switching between USB host and peripheral roles.391 A connector must be added as a subnode in that case.392 393 See ../connector/usb-connector.yaml.394 395 vbus-supply:396 description: A phandle to the regulator supplying the VBUS397 voltage.398 399 usb2-2:400 type: object401 additionalProperties: false402 properties:403 # no need to further describe this because the connector will404 # match on gpio-usb-b-connector or usb-b-connector and cause405 # that binding to be selected for the subnode406 connector:407 type: object408 409 mode:410 description: A string that determines the mode in which to411 run the port.412 $ref: /schemas/types.yaml#/definitions/string413 enum: [ host, peripheral, otg ]414 415 nvidia,internal:416 description: A boolean property whose presence determines417 that a port is internal. In the absence of this property418 the port is considered to be external.419 $ref: /schemas/types.yaml#/definitions/flag420 421 usb-role-switch:422 description: |423 A boolean property whole presence indicates that the port424 supports OTG or peripheral mode. If present, the port425 supports switching between USB host and peripheral roles.426 A connector must be added as a subnode in that case.427 428 See ../connector/usb-connector.yaml.429 430 vbus-supply:431 description: A phandle to the regulator supplying the VBUS432 voltage.433 434 ulpi-0:435 type: object436 additionalProperties: false437 properties:438 nvidia,internal:439 description: A boolean property whose presence determines440 that a port is internal. In the absence of this property441 the port is considered to be external.442 $ref: /schemas/types.yaml#/definitions/flag443 444 vbus-supply:445 description: A phandle to the regulator supplying the VBUS446 voltage.447 448 hsic-0:449 type: object450 additionalProperties: false451 properties:452 vbus-supply:453 description: A phandle to the regulator supplying the VBUS454 voltage.455 456 hsic-1:457 type: object458 additionalProperties: false459 properties:460 vbus-supply:461 description: A phandle to the regulator supplying the VBUS462 voltage.463 464 usb3-0:465 type: object466 additionalProperties: false467 properties:468 nvidia,internal:469 description: A boolean property whose presence determines470 that a port is internal. In the absence of this property471 the port is considered to be external.472 $ref: /schemas/types.yaml#/definitions/flag473 474 nvidia,usb2-companion:475 description: A single cell that specifies the physical port476 number to map this super-speed USB port to. The range of477 valid port numbers varies with the SoC generation.478 $ref: /schemas/types.yaml#/definitions/uint32479 enum: [ 0, 1, 2 ]480 481 vbus-supply:482 description: A phandle to the regulator supplying the VBUS483 voltage.484 485 usb3-1:486 type: object487 additionalProperties: false488 properties:489 nvidia,internal:490 description: A boolean property whose presence determines491 that a port is internal. In the absence of this property492 the port is considered to be external.493 $ref: /schemas/types.yaml#/definitions/flag494 495 nvidia,usb2-companion:496 description: A single cell that specifies the physical port497 number to map this super-speed USB port to. The range of498 valid port numbers varies with the SoC generation.499 $ref: /schemas/types.yaml#/definitions/uint32500 enum: [ 0, 1, 2 ]501 502 vbus-supply:503 description: A phandle to the regulator supplying the VBUS504 voltage.505 506additionalProperties: false507 508required:509 - compatible510 - reg511 - resets512 - reset-names513 - avdd-pll-utmip-supply514 - avdd-pll-erefe-supply515 - avdd-pex-pll-supply516 - hvdd-pex-pll-e-supply517 518examples:519 # Tegra124 and Tegra132520 - |521 #include <dt-bindings/interrupt-controller/arm-gic.h>522 523 padctl@7009f000 {524 compatible = "nvidia,tegra124-xusb-padctl";525 reg = <0x7009f000 0x1000>;526 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;527 resets = <&tegra_car 142>;528 reset-names = "padctl";529 530 avdd-pll-utmip-supply = <&vddio_1v8>;531 avdd-pll-erefe-supply = <&avdd_1v05_run>;532 avdd-pex-pll-supply = <&vdd_1v05_run>;533 hvdd-pex-pll-e-supply = <&vdd_3v3_lp0>;534 535 pads {536 usb2 {537 lanes {538 usb2-0 {539 nvidia,function = "xusb";540 #phy-cells = <0>;541 };542 543 usb2-1 {544 nvidia,function = "xusb";545 #phy-cells = <0>;546 };547 548 usb2-2 {549 nvidia,function = "xusb";550 #phy-cells = <0>;551 };552 };553 };554 555 ulpi {556 lanes {557 ulpi-0 {558 status = "disabled";559 #phy-cells = <0>;560 };561 };562 };563 564 hsic {565 lanes {566 hsic-0 {567 status = "disabled";568 #phy-cells = <0>;569 };570 571 hsic-1 {572 status = "disabled";573 #phy-cells = <0>;574 };575 };576 };577 578 pcie {579 lanes {580 pcie-0 {581 nvidia,function = "usb3-ss";582 #phy-cells = <0>;583 };584 585 pcie-1 {586 status = "disabled";587 #phy-cells = <0>;588 };589 590 pcie-2 {591 nvidia,function = "pcie";592 #phy-cells = <0>;593 };594 595 pcie-3 {596 status = "disabled";597 #phy-cells = <0>;598 };599 600 pcie-4 {601 nvidia,function = "pcie";602 #phy-cells = <0>;603 };604 };605 };606 607 sata {608 lanes {609 sata-0 {610 nvidia,function = "sata";611 #phy-cells = <0>;612 };613 };614 };615 };616 617 ports {618 /* Micro A/B */619 usb2-0 {620 mode = "otg";621 };622 623 /* Mini PCIe */624 usb2-1 {625 mode = "host";626 };627 628 /* USB3 */629 usb2-2 {630 vbus-supply = <&vdd_usb3_vbus>;631 mode = "host";632 };633 634 ulpi-0 {635 status = "disabled";636 };637 638 hsic-0 {639 status = "disabled";640 };641 642 hsic-1 {643 status = "disabled";644 };645 646 usb3-0 {647 nvidia,usb2-companion = <2>;648 };649 650 usb3-1 {651 status = "disabled";652 };653 };654 };655