374 lines · yaml
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)2%YAML 1.23---4$id: http://devicetree.org/schemas/phy/nvidia,tegra20-usb-phy.yaml#5$schema: http://devicetree.org/meta-schemas/core.yaml#6 7title: NVIDIA Tegra USB PHY8 9maintainers:10 - Dmitry Osipenko <digetx@gmail.com>11 - Jon Hunter <jonathanh@nvidia.com>12 - Thierry Reding <thierry.reding@gmail.com>13 14properties:15 compatible:16 oneOf:17 - items:18 - enum:19 - nvidia,tegra124-usb-phy20 - nvidia,tegra114-usb-phy21 - enum:22 - nvidia,tegra30-usb-phy23 - items:24 - enum:25 - nvidia,tegra30-usb-phy26 - nvidia,tegra20-usb-phy27 28 reg:29 minItems: 130 maxItems: 231 description: |32 PHY0 and PHY2 share power and ground, PHY0 contains shared registers.33 PHY0 and PHY2 must specify two register sets, where the first set is34 PHY own registers and the second set is the PHY0 registers.35 36 clocks:37 anyOf:38 - items:39 - description: Registers clock40 - description: Main PHY clock41 42 - items:43 - description: Registers clock44 - description: Main PHY clock45 - description: ULPI PHY clock46 47 - items:48 - description: Registers clock49 - description: Main PHY clock50 - description: UTMI pads control registers clock51 52 - items:53 - description: Registers clock54 - description: Main PHY clock55 - description: UTMI timeout clock56 - description: UTMI pads control registers clock57 58 clock-names:59 oneOf:60 - items:61 - const: reg62 - const: pll_u63 64 - items:65 - const: reg66 - const: pll_u67 - const: ulpi-link68 69 - items:70 - const: reg71 - const: pll_u72 - const: utmi-pads73 74 - items:75 - const: reg76 - const: pll_u77 - const: timer78 - const: utmi-pads79 80 interrupts:81 maxItems: 182 83 resets:84 oneOf:85 - maxItems: 186 description: PHY reset87 88 - items:89 - description: PHY reset90 - description: UTMI pads reset91 92 reset-names:93 oneOf:94 - const: usb95 96 - items:97 - const: usb98 - const: utmi-pads99 100 "#phy-cells":101 const: 0102 103 phy_type:104 $ref: /schemas/types.yaml#/definitions/string105 enum: [utmi, ulpi, hsic]106 107 dr_mode:108 $ref: /schemas/types.yaml#/definitions/string109 enum: [host, peripheral, otg]110 default: host111 112 vbus-supply:113 description: Regulator controlling USB VBUS.114 115 nvidia,has-legacy-mode:116 description: |117 Indicates whether this controller can operate in legacy mode118 (as APX 2500 / 2600). In legacy mode some registers are accessed119 through the APB_MISC base address instead of the USB controller.120 type: boolean121 122 nvidia,is-wired:123 description: |124 Indicates whether we can do certain kind of power optimizations for125 the devices that are always connected. e.g. modem.126 type: boolean127 128 nvidia,has-utmi-pad-registers:129 description: |130 Indicates whether this controller contains the UTMI pad control131 registers common to all USB controllers.132 type: boolean133 134 nvidia,hssync-start-delay:135 $ref: /schemas/types.yaml#/definitions/uint32136 minimum: 0137 maximum: 31138 description: |139 Number of 480 MHz clock cycles to wait before start of sync launches140 RxActive.141 142 nvidia,elastic-limit:143 $ref: /schemas/types.yaml#/definitions/uint32144 minimum: 0145 maximum: 31146 description: Variable FIFO Depth of elastic input store.147 148 nvidia,idle-wait-delay:149 $ref: /schemas/types.yaml#/definitions/uint32150 minimum: 0151 maximum: 31152 description: |153 Number of 480 MHz clock cycles of idle to wait before declare IDLE.154 155 nvidia,term-range-adj:156 $ref: /schemas/types.yaml#/definitions/uint32157 minimum: 0158 maximum: 15159 description: Range adjustment on terminations.160 161 nvidia,xcvr-setup:162 $ref: /schemas/types.yaml#/definitions/uint32163 minimum: 0164 maximum: 127165 description: Input of XCVR cell, HS driver output control.166 167 nvidia,xcvr-setup-use-fuses:168 description: Indicates that the value is read from the on-chip fuses.169 type: boolean170 171 nvidia,xcvr-lsfslew:172 $ref: /schemas/types.yaml#/definitions/uint32173 minimum: 0174 maximum: 3175 description: LS falling slew rate control.176 177 nvidia,xcvr-lsrslew:178 $ref: /schemas/types.yaml#/definitions/uint32179 minimum: 0180 maximum: 3181 description: LS rising slew rate control.182 183 nvidia,xcvr-hsslew:184 $ref: /schemas/types.yaml#/definitions/uint32185 minimum: 0186 maximum: 511187 description: HS slew rate control.188 189 nvidia,hssquelch-level:190 $ref: /schemas/types.yaml#/definitions/uint32191 minimum: 0192 maximum: 3193 description: HS squelch detector level.194 195 nvidia,hsdiscon-level:196 $ref: /schemas/types.yaml#/definitions/uint32197 minimum: 0198 maximum: 7199 description: HS disconnect detector level.200 201 nvidia,phy-reset-gpio:202 maxItems: 1203 description: GPIO used to reset the PHY.204 205 nvidia,pmc:206 $ref: /schemas/types.yaml#/definitions/phandle-array207 items:208 - items:209 - description: Phandle to Power Management controller.210 - description: USB controller ID.211 description:212 Phandle to Power Management controller.213 214required:215 - compatible216 - reg217 - clocks218 - clock-names219 - resets220 - reset-names221 - "#phy-cells"222 - phy_type223 224additionalProperties: false225 226allOf:227 - if:228 properties:229 phy_type:230 const: utmi231 232 then:233 properties:234 reg:235 minItems: 2236 maxItems: 2237 238 resets:239 maxItems: 2240 241 reset-names:242 maxItems: 2243 244 required:245 - nvidia,hssync-start-delay246 - nvidia,elastic-limit247 - nvidia,idle-wait-delay248 - nvidia,term-range-adj249 - nvidia,xcvr-lsfslew250 - nvidia,xcvr-lsrslew251 252 anyOf:253 - required: ["nvidia,xcvr-setup"]254 - required: ["nvidia,xcvr-setup-use-fuses"]255 256 if:257 properties:258 compatible:259 contains:260 const: nvidia,tegra30-usb-phy261 262 then:263 properties:264 clocks:265 maxItems: 3266 267 clock-names:268 items:269 - const: reg270 - const: pll_u271 - const: utmi-pads272 273 required:274 - nvidia,xcvr-hsslew275 - nvidia,hssquelch-level276 - nvidia,hsdiscon-level277 278 else:279 properties:280 clocks:281 maxItems: 4282 283 clock-names:284 items:285 - const: reg286 - const: pll_u287 - const: timer288 - const: utmi-pads289 290 - if:291 properties:292 phy_type:293 const: ulpi294 295 then:296 properties:297 reg:298 minItems: 1299 maxItems: 1300 301 clocks:302 minItems: 2303 maxItems: 3304 305 clock-names:306 minItems: 2307 maxItems: 3308 309 oneOf:310 - items:311 - const: reg312 - const: pll_u313 314 - items:315 - const: reg316 - const: pll_u317 - const: ulpi-link318 319 resets:320 minItems: 1321 maxItems: 2322 323 reset-names:324 minItems: 1325 maxItems: 2326 327examples:328 - |329 #include <dt-bindings/clock/tegra124-car.h>330 331 usb-phy@7d008000 {332 compatible = "nvidia,tegra124-usb-phy", "nvidia,tegra30-usb-phy";333 reg = <0x7d008000 0x4000>,334 <0x7d000000 0x4000>;335 interrupts = <0 97 4>;336 phy_type = "utmi";337 clocks = <&tegra_car TEGRA124_CLK_USB3>,338 <&tegra_car TEGRA124_CLK_PLL_U>,339 <&tegra_car TEGRA124_CLK_USBD>;340 clock-names = "reg", "pll_u", "utmi-pads";341 resets = <&tegra_car 59>, <&tegra_car 22>;342 reset-names = "usb", "utmi-pads";343 #phy-cells = <0>;344 nvidia,hssync-start-delay = <0>;345 nvidia,idle-wait-delay = <17>;346 nvidia,elastic-limit = <16>;347 nvidia,term-range-adj = <6>;348 nvidia,xcvr-setup = <9>;349 nvidia,xcvr-lsfslew = <0>;350 nvidia,xcvr-lsrslew = <3>;351 nvidia,hssquelch-level = <2>;352 nvidia,hsdiscon-level = <5>;353 nvidia,xcvr-hsslew = <12>;354 nvidia,pmc = <&tegra_pmc 2>;355 };356 357 - |358 #include <dt-bindings/clock/tegra20-car.h>359 360 usb-phy@c5004000 {361 compatible = "nvidia,tegra20-usb-phy";362 reg = <0xc5004000 0x4000>;363 interrupts = <0 21 4>;364 phy_type = "ulpi";365 clocks = <&tegra_car TEGRA20_CLK_USB2>,366 <&tegra_car TEGRA20_CLK_PLL_U>,367 <&tegra_car TEGRA20_CLK_CDEV2>;368 clock-names = "reg", "pll_u", "ulpi-link";369 resets = <&tegra_car 58>, <&tegra_car 22>;370 reset-names = "usb", "utmi-pads";371 #phy-cells = <0>;372 nvidia,pmc = <&tegra_pmc 1>;373 };374