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1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)2%YAML 1.23---4$id: http://devicetree.org/schemas/phy/phy-cadence-sierra.yaml#5$schema: http://devicetree.org/meta-schemas/core.yaml#6 7title: Cadence Sierra PHY8 9description:10 This binding describes the Cadence Sierra PHY. Sierra PHY supports multilink11 multiprotocol combinations including protocols such as PCIe, USB etc.12 13maintainers:14 - Swapnil Jakhade <sjakhade@cadence.com>15 - Yuti Amonkar <yamonkar@cadence.com>16 17properties:18 compatible:19 enum:20 - cdns,sierra-phy-t021 - ti,sierra-phy-t022 23 '#address-cells':24 const: 125 26 '#size-cells':27 const: 028 29 '#clock-cells':30 const: 131 32 resets:33 minItems: 134 items:35 - description: Sierra PHY reset.36 - description: Sierra APB reset. This is optional.37 38 reset-names:39 minItems: 140 items:41 - const: sierra_reset42 - const: sierra_apb43 44 reg:45 maxItems: 146 description:47 Offset of the Sierra PHY configuration registers.48 49 reg-names:50 const: serdes51 52 clocks:53 minItems: 254 maxItems: 455 56 clock-names:57 minItems: 258 items:59 - const: cmn_refclk_dig_div60 - const: cmn_refclk1_dig_div61 - const: pll0_refclk62 - const: pll1_refclk63 64 cdns,autoconf:65 type: boolean66 description:67 A boolean property whose presence indicates that the PHY registers will be68 configured by hardware. If not present, all sub-node optional properties69 must be provided.70 71patternProperties:72 '^phy@[0-9a-f]$':73 type: object74 description:75 Each group of PHY lanes with a single master lane should be represented as76 a sub-node. Note that the actual configuration of each lane is determined77 by hardware strapping, and must match the configuration specified here.78 properties:79 reg:80 description:81 The master lane number. This is the lowest numbered lane in the lane group.82 minimum: 083 maximum: 1584 85 resets:86 minItems: 187 maxItems: 488 description:89 Contains list of resets, one per lane, to get all the link lanes out of reset.90 91 "#phy-cells":92 const: 093 94 cdns,phy-type:95 description:96 Specifies the type of PHY for which the group of PHY lanes is used.97 Refer include/dt-bindings/phy/phy.h. Constants from the header should be used.98 $ref: /schemas/types.yaml#/definitions/uint3299 enum: [2, 4]100 101 cdns,num-lanes:102 description:103 Number of lanes in this group. The group is made up of consecutive lanes.104 $ref: /schemas/types.yaml#/definitions/uint32105 minimum: 1106 maximum: 16107 108 cdns,ssc-mode:109 description:110 Specifies the Spread Spectrum Clocking mode used. It can be NO_SSC,111 EXTERNAL_SSC or INTERNAL_SSC.112 Refer include/dt-bindings/phy/phy-cadence.h for the constants to be used.113 $ref: /schemas/types.yaml#/definitions/uint32114 enum: [0, 1, 2]115 default: 1116 117 required:118 - reg119 - resets120 - "#phy-cells"121 122 additionalProperties: false123 124required:125 - compatible126 - "#address-cells"127 - "#size-cells"128 - reg129 - resets130 - reset-names131 132additionalProperties: false133 134examples:135 - |136 #include <dt-bindings/phy/phy.h>137 138 bus {139 #address-cells = <2>;140 #size-cells = <2>;141 142 sierra-phy@fd240000 {143 compatible = "cdns,sierra-phy-t0";144 reg = <0x0 0xfd240000 0x0 0x40000>;145 resets = <&phyrst 0>, <&phyrst 1>;146 reset-names = "sierra_reset", "sierra_apb";147 clocks = <&cmn_refclk_dig_div>, <&cmn_refclk1_dig_div>;148 clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div";149 #address-cells = <1>;150 #size-cells = <0>;151 pcie0_phy0: phy@0 {152 reg = <0>;153 resets = <&phyrst 2>;154 cdns,num-lanes = <2>;155 #phy-cells = <0>;156 cdns,phy-type = <PHY_TYPE_PCIE>;157 };158 pcie0_phy1: phy@2 {159 reg = <2>;160 resets = <&phyrst 4>;161 cdns,num-lanes = <1>;162 #phy-cells = <0>;163 cdns,phy-type = <PHY_TYPE_PCIE>;164 };165 };166 };167