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1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)2%YAML 1.23---4$id: http://devicetree.org/schemas/phy/phy-cadence-torrent.yaml#5$schema: http://devicetree.org/meta-schemas/core.yaml#6 7title: Cadence Torrent SD0801 PHY8 9description:10 This binding describes the Cadence SD0801 PHY (also known as Torrent PHY)11 hardware included with the Cadence MHDP DisplayPort controller. Torrent12 PHY also supports multilink multiprotocol combinations including protocols13 such as PCIe, USB, SGMII, QSGMII etc.14 15maintainers:16 - Swapnil Jakhade <sjakhade@cadence.com>17 - Yuti Amonkar <yamonkar@cadence.com>18 19properties:20 compatible:21 enum:22 - cdns,torrent-phy23 - ti,j7200-serdes-10g24 - ti,j721e-serdes-10g25 26 '#address-cells':27 const: 128 29 '#size-cells':30 const: 031 32 '#clock-cells':33 const: 134 35 clocks:36 minItems: 137 maxItems: 238 description:39 PHY input reference clocks - refclk (for PLL0) & pll1_refclk (for PLL1).40 pll1_refclk is optional and used for multi-protocol configurations requiring41 separate reference clock for each protocol.42 Same refclk is used for both PLL0 and PLL1 if no separate pll1_refclk is used.43 Optional parent clock (phy_en_refclk) to enable a reference clock output feature44 on some platforms to output either derived or received reference clock.45 46 clock-names:47 minItems: 148 items:49 - const: refclk50 - enum: [ pll1_refclk, phy_en_refclk ]51 52 reg:53 minItems: 154 items:55 - description: Offset of the Torrent PHY configuration registers.56 - description: Offset of the DPTX PHY configuration registers.57 58 reg-names:59 minItems: 160 items:61 - const: torrent_phy62 - const: dptx_phy63 64 resets:65 minItems: 166 items:67 - description: Torrent PHY reset.68 - description: Torrent APB reset. This is optional.69 70 reset-names:71 minItems: 172 items:73 - const: torrent_reset74 - const: torrent_apb75 76patternProperties:77 '^phy@[0-3]$':78 type: object79 description:80 Each group of PHY lanes with a single master lane should be represented as a sub-node.81 properties:82 reg:83 description:84 The master lane number. This is the lowest numbered lane in the lane group.85 minimum: 086 maximum: 387 88 resets:89 minItems: 190 maxItems: 491 description:92 Contains list of resets, one per lane, to get all the link lanes out of reset.93 94 "#phy-cells":95 const: 096 97 cdns,phy-type:98 description:99 Specifies the type of PHY for which the group of PHY lanes is used.100 Refer include/dt-bindings/phy/phy.h. Constants from the header should be used.101 $ref: /schemas/types.yaml#/definitions/uint32102 minimum: 1103 maximum: 9104 105 cdns,num-lanes:106 description:107 Number of lanes.108 $ref: /schemas/types.yaml#/definitions/uint32109 enum: [1, 2, 3, 4]110 default: 4111 112 cdns,ssc-mode:113 description:114 Specifies the Spread Spectrum Clocking mode used. It can be NO_SSC,115 EXTERNAL_SSC or INTERNAL_SSC.116 Refer include/dt-bindings/phy/phy-cadence.h for the constants to be used.117 $ref: /schemas/types.yaml#/definitions/uint32118 enum: [0, 1, 2]119 default: 0120 121 cdns,max-bit-rate:122 description:123 Maximum DisplayPort link bit rate to use, in Mbps124 $ref: /schemas/types.yaml#/definitions/uint32125 enum: [2160, 2430, 2700, 3240, 4320, 5400, 8100]126 default: 8100127 128 required:129 - reg130 - resets131 - "#phy-cells"132 - cdns,phy-type133 - cdns,num-lanes134 135 additionalProperties: false136 137required:138 - compatible139 - "#address-cells"140 - "#size-cells"141 - clocks142 - clock-names143 - reg144 - reg-names145 - resets146 - reset-names147 148additionalProperties: false149 150examples:151 - |152 #include <dt-bindings/phy/phy.h>153 154 bus {155 #address-cells = <2>;156 #size-cells = <2>;157 158 torrent-phy@f0fb500000 {159 compatible = "cdns,torrent-phy";160 reg = <0xf0 0xfb500000 0x0 0x00100000>,161 <0xf0 0xfb030a00 0x0 0x00000040>;162 reg-names = "torrent_phy", "dptx_phy";163 resets = <&phyrst 0>;164 reset-names = "torrent_reset";165 clocks = <&ref_clk>;166 clock-names = "refclk";167 #address-cells = <1>;168 #size-cells = <0>;169 phy@0 {170 reg = <0>;171 resets = <&phyrst 1>, <&phyrst 2>,172 <&phyrst 3>, <&phyrst 4>;173 #phy-cells = <0>;174 cdns,phy-type = <PHY_TYPE_DP>;175 cdns,num-lanes = <4>;176 cdns,max-bit-rate = <8100>;177 };178 };179 };180 - |181 #include <dt-bindings/phy/phy.h>182 #include <dt-bindings/phy/phy-cadence.h>183 184 bus {185 #address-cells = <2>;186 #size-cells = <2>;187 188 torrent-phy@f0fb500000 {189 compatible = "cdns,torrent-phy";190 reg = <0xf0 0xfb500000 0x0 0x00100000>;191 reg-names = "torrent_phy";192 resets = <&phyrst 0>, <&phyrst 1>;193 reset-names = "torrent_reset", "torrent_apb";194 clocks = <&ref_clk>;195 clock-names = "refclk";196 #address-cells = <1>;197 #size-cells = <0>;198 phy@0 {199 reg = <0>;200 resets = <&phyrst 2>, <&phyrst 3>;201 #phy-cells = <0>;202 cdns,phy-type = <PHY_TYPE_PCIE>;203 cdns,num-lanes = <2>;204 cdns,ssc-mode = <CDNS_SERDES_NO_SSC>;205 };206 207 phy@2 {208 reg = <2>;209 resets = <&phyrst 4>;210 #phy-cells = <0>;211 cdns,phy-type = <PHY_TYPE_SGMII>;212 cdns,num-lanes = <1>;213 cdns,ssc-mode = <CDNS_SERDES_NO_SSC>;214 };215 };216 };217...218