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1STMicroelectronics STi MIPHY28LP PHY binding2============================================3 4This binding describes a miphy device that is used to control PHY hardware5for SATA, PCIe or USB3.6 7Required properties (controller (parent) node):8- compatible : Should be "st,miphy28lp-phy".9- st,syscfg : Should be a phandle of the system configuration register group10 which contain the SATA, PCIe or USB3 mode setting bits.11 12Required nodes : A sub-node is required for each channel the controller13 provides. Address range information including the usual14 'reg' and 'reg-names' properties are used inside these15 nodes to describe the controller's topology. These nodes16 are translated by the driver's .xlate() function.17 18Required properties (port (child) node):19- #phy-cells : Should be 1 (See second example)20 Cell after port phandle is device type from:21 - PHY_TYPE_SATA22 - PHY_TYPE_PCI23 - PHY_TYPE_USB324- reg : Address and length of the register set for the device.25- reg-names : The names of the register addresses corresponding to the registers26 filled in "reg". It can also contain the offset of the system configuration27 registers used as glue-logic to setup the device for SATA/PCIe or USB328 devices.29- st,syscfg : Offset of the parent configuration register.30- resets : phandle to the parent reset controller.31- reset-names : Associated name must be "miphy-sw-rst".32 33Optional properties (port (child) node):34- st,osc-rdy : to check the MIPHY0_OSC_RDY status in the glue-logic. This35 is not available in all the MiPHY. For example, for STiH407, only the36 MiPHY0 has this bit.37- st,osc-force-ext : to select the external oscillator. This can change from38 different MiPHY inside the same SoC.39- st,sata_gen : to select which SATA_SPDMODE has to be set in the SATA system config40 register.41- st,px_rx_pol_inv : to invert polarity of RXn/RXp (respectively negative line and positive42 line).43- st,scc-on : enable ssc to reduce effects of EMI (only for sata or PCIe).44- st,tx-impedance-comp : to compensate tx impedance avoiding out of range values.45 46example:47 48 miphy28lp_phy: miphy28lp@9b22000 {49 compatible = "st,miphy28lp-phy";50 st,syscfg = <&syscfg_core>;51 #address-cells = <1>;52 #size-cells = <1>;53 ranges;54 55 phy_port0: port@9b22000 {56 reg = <0x9b22000 0xff>,57 <0x9b09000 0xff>,58 <0x9b04000 0xff>;59 reg-names = "sata-up",60 "pcie-up",61 "pipew";62 63 st,syscfg = <0x114 0x818 0xe0 0xec>;64 #phy-cells = <1>;65 st,osc-rdy;66 reset-names = "miphy-sw-rst";67 resets = <&softreset STIH407_MIPHY0_SOFTRESET>;68 };69 70 phy_port1: port@9b2a000 {71 reg = <0x9b2a000 0xff>,72 <0x9b19000 0xff>,73 <0x9b14000 0xff>;74 reg-names = "sata-up",75 "pcie-up",76 "pipew";77 78 st,syscfg = <0x118 0x81c 0xe4 0xf0>;79 80 #phy-cells = <1>;81 st,osc-force-ext;82 reset-names = "miphy-sw-rst";83 resets = <&softreset STIH407_MIPHY1_SOFTRESET>;84 };85 86 phy_port2: port@8f95000 {87 reg = <0x8f95000 0xff>,88 <0x8f90000 0xff>;89 reg-names = "pipew",90 "usb3-up";91 92 st,syscfg = <0x11c 0x820>;93 94 #phy-cells = <1>;95 reset-names = "miphy-sw-rst";96 resets = <&softreset STIH407_MIPHY2_SOFTRESET>;97 };98 };99 100 101Specifying phy control of devices102=================================103 104Device nodes should specify the configuration required in their "phys"105property, containing a phandle to the miphy device node and an index106specifying which configuration to use, as described in phy-bindings.txt.107 108example:109 sata0: sata@9b20000 {110 ...111 phys = <&phy_port0 PHY_TYPE_SATA>;112 ...113 };114 115Macro definitions for the supported miphy configuration can be found in:116 117include/dt-bindings/phy/phy.h118