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1STMicroelectronics STi MIPHY365x PHY binding2============================================3 4This binding describes a miphy device that is used to control PHY hardware5for SATA and PCIe.6 7Required properties (controller (parent) node):8- compatible : Should be "st,miphy365x-phy"9- st,syscfg : Phandle / integer array property. Phandle of sysconfig group10 containing the miphy registers and integer array should contain11 an entry for each port sub-node, specifying the control12 register offset inside the sysconfig group.13 14Required nodes : A sub-node is required for each channel the controller15 provides. Address range information including the usual16 'reg' and 'reg-names' properties are used inside these17 nodes to describe the controller's topology. These nodes18 are translated by the driver's .xlate() function.19 20Required properties (port (child) node):21- #phy-cells : Should be 1 (See second example)22 Cell after port phandle is device type from:23 - PHY_TYPE_SATA24 - PHY_TYPE_PCI25- reg : Address and length of register sets for each device in26 "reg-names"27- reg-names : The names of the register addresses corresponding to the28 registers filled in "reg":29 - sata: For SATA devices30 - pcie: For PCIe devices31 32Optional properties (port (child) node):33- st,sata-gen : Generation of locally attached SATA IP. Expected values34 are {1,2,3). If not supplied generation 1 hardware will35 be expected36- st,pcie-tx-pol-inv : Bool property to invert the polarity PCIe Tx (Txn/Txp)37- st,sata-tx-pol-inv : Bool property to invert the polarity SATA Tx (Txn/Txp)38 39Example:40 41 miphy365x_phy: miphy365x@fe382000 {42 compatible = "st,miphy365x-phy";43 st,syscfg = <&syscfg_rear 0x824 0x828>;44 #address-cells = <1>;45 #size-cells = <1>;46 ranges;47 48 phy_port0: port@fe382000 {49 reg = <0xfe382000 0x100>, <0xfe394000 0x100>;50 reg-names = "sata", "pcie";51 #phy-cells = <1>;52 st,sata-gen = <3>;53 };54 55 phy_port1: port@fe38a000 {56 reg = <0xfe38a000 0x100>, <0xfe804000 0x100>;;57 reg-names = "sata", "pcie", "syscfg";58 #phy-cells = <1>;59 st,pcie-tx-pol-inv;60 };61 };62 63Specifying phy control of devices64=================================65 66Device nodes should specify the configuration required in their "phys"67property, containing a phandle to the phy port node and a device type.68 69Example:70 71#include <dt-bindings/phy/phy.h>72 73 sata0: sata@fe380000 {74 ...75 phys = <&phy_port0 PHY_TYPE_SATA>;76 ...77 };78