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1MVEBU comphy drivers2--------------------3 4COMPHY controllers can be found on the following Marvell MVEBU SoCs:5* Armada 7k/8k (on the CP110)6* Armada 37007It provides a number of shared PHYs used by various interfaces (network, SATA,8USB, PCIe...).9 10Required properties:11 12- compatible: should be one of:13 * "marvell,comphy-cp110" for Armada 7k/8k14 * "marvell,comphy-a3700" for Armada 370015- reg: should contain the COMPHY register(s) location(s) and length(s).16 * 1 entry for Armada 7k/8k17 * 4 entries for Armada 3700 along with the corresponding reg-names18 properties, memory areas are:19 * Generic COMPHY registers20 * Lane 1 (PCIe/GbE)21 * Lane 0 (USB3/GbE)22 * Lane 2 (SATA/USB3)23- marvell,system-controller: should contain a phandle to the system24 controller node (only for Armada 7k/8k)25- #address-cells: should be 1.26- #size-cells: should be 0.27 28Optional properlties:29 30- clocks: pointers to the reference clocks for this device (CP110 only),31 consequently: MG clock, MG Core clock, AXI clock.32- clock-names: names of used clocks for CP110 only, must be :33 "mg_clk", "mg_core_clk" and "axi_clk".34 35A sub-node is required for each comphy lane provided by the comphy.36 37Required properties (child nodes):38 39- reg: COMPHY lane number.40- #phy-cells : from the generic PHY bindings, must be 1. Defines the41 input port to use for a given comphy lane.42 43Examples:44 45 CP11X_LABEL(comphy): phy@120000 {46 compatible = "marvell,comphy-cp110";47 reg = <0x120000 0x6000>;48 marvell,system-controller = <&CP11X_LABEL(syscon0)>;49 clocks = <&CP11X_LABEL(clk) 1 5>, <&CP11X_LABEL(clk) 1 6>,50 <&CP11X_LABEL(clk) 1 18>;51 clock-names = "mg_clk", "mg_core_clk", "axi_clk";52 #address-cells = <1>;53 #size-cells = <0>;54 55 CP11X_LABEL(comphy0): phy@0 {56 reg = <0>;57 #phy-cells = <1>;58 };59 60 CP11X_LABEL(comphy1): phy@1 {61 reg = <1>;62 #phy-cells = <1>;63 };64 };65 66 comphy: phy@18300 {67 compatible = "marvell,comphy-a3700";68 reg = <0x18300 0x300>,69 <0x1F000 0x400>,70 <0x5C000 0x400>,71 <0xe0178 0x8>;72 reg-names = "comphy",73 "lane1_pcie_gbe",74 "lane0_usb3_gbe",75 "lane2_sata_usb3";76 #address-cells = <1>;77 #size-cells = <0>;78 79 80 comphy0: phy@0 {81 reg = <0>;82 #phy-cells = <1>;83 };84 85 comphy1: phy@1 {86 reg = <1>;87 #phy-cells = <1>;88 };89 90 comphy2: phy@2 {91 reg = <2>;92 #phy-cells = <1>;93 };94 };95