143 lines · yaml
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)2%YAML 1.23---4$id: http://devicetree.org/schemas/phy/phy-rockchip-naneng-combphy.yaml#5$schema: http://devicetree.org/meta-schemas/core.yaml#6 7title: Rockchip SoC Naneng Combo Phy8 9maintainers:10 - Heiko Stuebner <heiko@sntech.de>11 12properties:13 compatible:14 enum:15 - rockchip,rk3568-naneng-combphy16 - rockchip,rk3588-naneng-combphy17 18 reg:19 maxItems: 120 21 clocks:22 items:23 - description: reference clock24 - description: apb clock25 - description: pipe clock26 27 clock-names:28 items:29 - const: ref30 - const: apb31 - const: pipe32 33 resets:34 minItems: 135 maxItems: 236 37 reset-names:38 minItems: 139 items:40 - const: phy41 - const: apb42 43 rockchip,enable-ssc:44 type: boolean45 description:46 The option SSC can be enabled for U3, SATA and PCIE.47 Most commercially available platforms use SSC to reduce EMI.48 49 rockchip,ext-refclk:50 type: boolean51 description:52 Many PCIe connections, especially backplane connections,53 require a synchronous reference clock between the two link partners.54 To achieve this a common clock source, referred to as REFCLK in55 the PCI Express Card Electromechanical Specification,56 should be used by both ends of the PCIe link.57 In PCIe mode one can choose to use an internal or an external reference58 clock.59 By default the internal clock is selected. The PCIe PHY provides a 100MHz60 differential clock output(optional with SSC) for system applications.61 When selecting this option an externally 100MHz differential62 reference clock needs to be provided to the PCIe PHY.63 64 rockchip,pipe-grf:65 $ref: /schemas/types.yaml#/definitions/phandle66 description:67 Some additional phy settings are accessed through GRF regs.68 69 rockchip,pipe-phy-grf:70 $ref: /schemas/types.yaml#/definitions/phandle71 description:72 Some additional pipe settings are accessed through GRF regs.73 74 "#phy-cells":75 const: 176 77required:78 - compatible79 - reg80 - clocks81 - clock-names82 - resets83 - rockchip,pipe-grf84 - rockchip,pipe-phy-grf85 - "#phy-cells"86 87allOf:88 - if:89 properties:90 compatible:91 contains:92 const: rockchip,rk3568-naneng-combphy93 then:94 properties:95 resets:96 maxItems: 197 reset-names:98 maxItems: 199 - if:100 properties:101 compatible:102 contains:103 const: rockchip,rk3588-naneng-combphy104 then:105 properties:106 resets:107 minItems: 2108 reset-names:109 minItems: 2110 required:111 - reset-names112 113additionalProperties: false114 115examples:116 - |117 #include <dt-bindings/clock/rk3568-cru.h>118 119 pipegrf: syscon@fdc50000 {120 compatible = "rockchip,rk3568-pipe-grf", "syscon";121 reg = <0xfdc50000 0x1000>;122 };123 124 pipe_phy_grf0: syscon@fdc70000 {125 compatible = "rockchip,rk3568-pipe-phy-grf", "syscon";126 reg = <0xfdc70000 0x1000>;127 };128 129 combphy0: phy@fe820000 {130 compatible = "rockchip,rk3568-naneng-combphy";131 reg = <0xfe820000 0x100>;132 clocks = <&pmucru CLK_PCIEPHY0_REF>,133 <&cru PCLK_PIPEPHY0>,134 <&cru PCLK_PIPE>;135 clock-names = "ref", "apb", "pipe";136 assigned-clocks = <&pmucru CLK_PCIEPHY0_REF>;137 assigned-clock-rates = <100000000>;138 resets = <&cru SRST_PIPEPHY0>;139 rockchip,pipe-grf = <&pipegrf>;140 rockchip,pipe-phy-grf = <&pipe_phy_grf0>;141 #phy-cells = <1>;142 };143