287 lines · yaml
1# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause2%YAML 1.23---4$id: http://devicetree.org/schemas/phy/phy-stm32-usbphyc.yaml#5$schema: http://devicetree.org/meta-schemas/core.yaml#6 7title: STMicroelectronics STM32 USB HS PHY controller8 9description:10 11 The STM32 USBPHYC block contains a dual port High Speed UTMI+ PHY and a UTMI12 switch. It controls PHY configuration and status, and the UTMI+ switch that13 selects either OTG or HOST controller for the second PHY port. It also sets14 PLL configuration.15 16 USBPHYC17 |_ PLL18 |19 |_ PHY port#1 _________________ HOST controller20 | __ |21 | / 1|________________|22 |_ PHY port#2 ----| |________________23 | \_0| |24 |_ UTMI switch_______| OTG controller25 26maintainers:27 - Amelie Delaunay <amelie.delaunay@foss.st.com>28 29properties:30 compatible:31 const: st,stm32mp1-usbphyc32 33 reg:34 maxItems: 135 36 clocks:37 maxItems: 138 39 resets:40 maxItems: 141 42 "#address-cells":43 const: 144 45 "#size-cells":46 const: 047 48 vdda1v1-supply:49 description: regulator providing 1V1 power supply to the PLL block50 51 vdda1v8-supply:52 description: regulator providing 1V8 power supply to the PLL block53 54 '#clock-cells':55 description: number of clock cells for ck_usbo_48m consumer56 const: 057 58 access-controllers:59 minItems: 160 maxItems: 261 62# Required child nodes:63 64patternProperties:65 "^usb-phy@[0|1]$":66 type: object67 description:68 Each port the controller provides must be represented as a sub-node.69 70 properties:71 reg:72 description: phy port index.73 maxItems: 174 75 phy-supply:76 description: regulator providing 3V3 power supply to the PHY.77 78 "#phy-cells":79 enum: [ 0x0, 0x1 ]80 81 connector:82 type: object83 $ref: /schemas/connector/usb-connector.yaml84 unevaluatedProperties: false85 86 properties:87 vbus-supply: true88 89 # It can be necessary to adjust the PHY settings to compensate parasitics, which can be due90 # to USB connector/receptacle, routing, ESD protection component,... Here is the list of91 # all optional parameters to tune the interface of the PHY (HS for High-Speed, FS for Full-92 # Speed, LS for Low-Speed)93 94 st,current-boost-microamp:95 description: Current boosting in uA96 enum: [ 1000, 2000 ]97 98 st,no-lsfs-fb-cap:99 description: Disables the LS/FS feedback capacitor100 type: boolean101 102 st,decrease-hs-slew-rate:103 description: Decreases the HS driver slew rate by 10%104 type: boolean105 106 st,tune-hs-dc-level:107 description: |108 Tunes the HS driver DC level109 - <0> normal level110 - <1> increases the level by 5 to 7 mV111 - <2> increases the level by 10 to 14 mV112 - <3> decreases the level by 5 to 7 mV113 $ref: /schemas/types.yaml#/definitions/uint32114 minimum: 0115 maximum: 3116 default: 0117 118 st,enable-fs-rftime-tuning:119 description: Enables the FS rise/fall tuning option120 type: boolean121 122 st,enable-hs-rftime-reduction:123 description: Enables the HS rise/fall reduction feature124 type: boolean125 126 st,trim-hs-current:127 description: |128 Controls HS driver current trimming for choke compensation129 - <0> = 18.87 mA target current / nominal + 0%130 - <1> = 19.165 mA target current / nominal + 1.56%131 - <2> = 19.46 mA target current / nominal + 3.12%132 - <3> = 19.755 mA target current / nominal + 4.68%133 - <4> = 20.05 mA target current / nominal + 6.24%134 - <5> = 20.345 mA target current / nominal + 7.8%135 - <6> = 20.64 mA target current / nominal + 9.36%136 - <7> = 20.935 mA target current / nominal + 10.92%137 - <8> = 21.23 mA target current / nominal + 12.48%138 - <9> = 21.525 mA target current / nominal + 14.04%139 - <10> = 21.82 mA target current / nominal + 15.6%140 - <11> = 22.115 mA target current / nominal + 17.16%141 - <12> = 22.458 mA target current / nominal + 19.01%142 - <13> = 22.755 mA target current / nominal + 20.58%143 - <14> = 23.052 mA target current / nominal + 22.16%144 - <15> = 23.348 mA target current / nominal + 23.73%145 $ref: /schemas/types.yaml#/definitions/uint32146 minimum: 0147 maximum: 15148 default: 0149 150 st,trim-hs-impedance:151 description: |152 Controls HS driver impedance tuning for choke compensation153 - <0> = no impedance offset154 - <1> = reduce the impedance by 2 ohms155 - <2> = reduce the impedance by 4 ohms156 - <3> = reduce the impedance by 6 ohms157 $ref: /schemas/types.yaml#/definitions/uint32158 minimum: 0159 maximum: 3160 default: 0161 162 st,tune-squelch-level:163 description: |164 Tunes the squelch DC threshold value165 - <0> = no shift in threshold166 - <1> = threshold shift by +7 mV167 - <2> = threshold shift by -5 mV168 - <3> = threshold shift by +14 mV169 $ref: /schemas/types.yaml#/definitions/uint32170 minimum: 0171 maximum: 3172 default: 0173 174 st,enable-hs-rx-gain-eq:175 description: Enables the HS Rx gain equalizer176 type: boolean177 178 st,tune-hs-rx-offset:179 description: |180 Adjusts the HS Rx offset181 - <0> = no offset182 - <1> = offset of +5 mV183 - <2> = offset of +10 mV184 - <3> = offset of -5 mV185 $ref: /schemas/types.yaml#/definitions/uint32186 minimum: 0187 maximum: 3188 default: 0189 190 st,no-hs-ftime-ctrl:191 description: Disables the HS fall time control of single ended signals during pre-emphasis192 type: boolean193 194 st,no-lsfs-sc:195 description: Disables the short circuit protection in LS/FS driver196 type: boolean197 198 st,enable-hs-tx-staggering:199 description: Enables the basic staggering in HS Tx mode200 type: boolean201 202 allOf:203 - if:204 properties:205 reg:206 const: 0207 then:208 properties:209 "#phy-cells":210 const: 0211 else:212 properties:213 "#phy-cells":214 const: 1215 description:216 The value is used to select UTMI switch output.217 0 for OTG controller and 1 for Host controller.218 219 required:220 - reg221 - phy-supply222 - "#phy-cells"223 224 additionalProperties: false225 226required:227 - compatible228 - reg229 - clocks230 - "#address-cells"231 - "#size-cells"232 - vdda1v1-supply233 - vdda1v8-supply234 - usb-phy@0235 - usb-phy@1236 237additionalProperties: false238 239examples:240 - |241 #include <dt-bindings/clock/stm32mp1-clks.h>242 #include <dt-bindings/reset/stm32mp1-resets.h>243 usbphyc: usbphyc@5a006000 {244 compatible = "st,stm32mp1-usbphyc";245 reg = <0x5a006000 0x1000>;246 clocks = <&rcc USBPHY_K>;247 resets = <&rcc USBPHY_R>;248 vdda1v1-supply = <®11>;249 vdda1v8-supply = <®18>;250 #address-cells = <1>;251 #size-cells = <0>;252 #clock-cells = <0>;253 254 usbphyc_port0: usb-phy@0 {255 reg = <0>;256 phy-supply = <&vdd_usb>;257 #phy-cells = <0>;258 st,tune-hs-dc-level = <2>;259 st,enable-fs-rftime-tuning;260 st,enable-hs-rftime-reduction;261 st,trim-hs-current = <15>;262 st,trim-hs-impedance = <1>;263 st,tune-squelch-level = <3>;264 st,tune-hs-rx-offset = <2>;265 st,no-lsfs-sc;266 connector {267 compatible = "usb-a-connector";268 vbus-supply = <&vbus_sw>;269 };270 };271 272 usbphyc_port1: usb-phy@1 {273 reg = <1>;274 phy-supply = <&vdd_usb>;275 #phy-cells = <1>;276 st,tune-hs-dc-level = <2>;277 st,enable-fs-rftime-tuning;278 st,enable-hs-rftime-reduction;279 st,trim-hs-current = <15>;280 st,trim-hs-impedance = <1>;281 st,tune-squelch-level = <3>;282 st,tune-hs-rx-offset = <2>;283 st,no-lsfs-sc;284 };285 };286...287