75 lines · yaml
1# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause2%YAML 1.23---4$id: http://devicetree.org/schemas/phy/qcom,ipq806x-usb-phy-ss.yaml#5$schema: http://devicetree.org/meta-schemas/core.yaml#6 7title: Qualcomm ipq806x usb DWC3 SS PHY CONTROLLER8 9maintainers:10 - Ansuel Smith <ansuelsmth@gmail.com>11 12description:13 DWC3 PHY nodes are defined to describe on-chip Synopsis Physical layer14 controllers used in ipq806x. Each DWC3 PHY controller should have its15 own node.16 17properties:18 compatible:19 const: qcom,ipq806x-usb-phy-ss20 21 "#phy-cells":22 const: 023 24 reg:25 maxItems: 126 27 clocks:28 minItems: 129 maxItems: 230 31 clock-names:32 minItems: 133 items:34 - const: ref35 - const: xo36 37 qcom,rx-eq:38 $ref: /schemas/types.yaml#/definitions/uint3239 description: Override value for rx_eq.40 default: 441 maximum: 742 43 qcom,tx-deamp-3_5db:44 $ref: /schemas/types.yaml#/definitions/uint3245 description: Override value for transmit preemphasis.46 default: 2347 maximum: 6348 49 qcom,mpll:50 $ref: /schemas/types.yaml#/definitions/uint3251 description: Override value for mpll.52 default: 053 maximum: 754 55required:56 - compatible57 - "#phy-cells"58 - reg59 - clocks60 - clock-names61 62additionalProperties: false63 64examples:65 - |66 #include <dt-bindings/clock/qcom,gcc-ipq806x.h>67 68 ss_phy_0: phy@110f8830 {69 compatible = "qcom,ipq806x-usb-phy-ss";70 reg = <0x110f8830 0x30>;71 clocks = <&gcc USB30_0_MASTER_CLK>;72 clock-names = "ref";73 #phy-cells = <0>;74 };75