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1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)2%YAML 1.23---4$id: http://devicetree.org/schemas/phy/qcom,msm8996-qmp-pcie-phy.yaml#5$schema: http://devicetree.org/meta-schemas/core.yaml#6 7title: Qualcomm QMP PHY controller (MSM8996 PCIe)8 9maintainers:10 - Vinod Koul <vkoul@kernel.org>11 12description:13 QMP PHY controller supports physical layer functionality for a number of14 controllers on Qualcomm chipsets, such as, PCIe, UFS, and USB.15 16properties:17 compatible:18 const: qcom,msm8996-qmp-pcie-phy19 20 reg:21 items:22 - description: serdes23 24 "#address-cells":25 enum: [ 1, 2 ]26 27 "#size-cells":28 enum: [ 1, 2 ]29 30 ranges: true31 32 clocks:33 maxItems: 334 35 clock-names:36 items:37 - const: aux38 - const: cfg_ahb39 - const: ref40 41 resets:42 maxItems: 343 44 reset-names:45 items:46 - const: phy47 - const: common48 - const: cfg49 50 vdda-phy-supply: true51 52 vdda-pll-supply: true53 54 vddp-ref-clk-supply: true55 56patternProperties:57 "^phy@[0-9a-f]+$":58 type: object59 description: one child node per PHY provided by this block60 properties:61 reg:62 items:63 - description: TX64 - description: RX65 - description: PCS66 67 clocks:68 items:69 - description: PIPE clock70 71 clock-names:72 deprecated: true73 items:74 - enum:75 - pipe076 - pipe177 - pipe278 79 resets:80 items:81 - description: PHY reset82 83 reset-names:84 deprecated: true85 items:86 - enum:87 - lane088 - lane189 - lane290 91 "#clock-cells":92 const: 093 94 clock-output-names:95 maxItems: 196 97 "#phy-cells":98 const: 099 100 required:101 - reg102 - clocks103 - resets104 - "#clock-cells"105 - clock-output-names106 - "#phy-cells"107 108 additionalProperties: false109 110required:111 - compatible112 - reg113 - "#address-cells"114 - "#size-cells"115 - ranges116 - clocks117 - clock-names118 - resets119 - reset-names120 - vdda-phy-supply121 - vdda-pll-supply122 123additionalProperties: false124 125examples:126 - |127 #include <dt-bindings/clock/qcom,gcc-msm8996.h>128 pcie_phy: phy-wrapper@34000 {129 compatible = "qcom,msm8996-qmp-pcie-phy";130 reg = <0x34000 0x488>;131 #address-cells = <1>;132 #size-cells = <1>;133 ranges = <0x0 0x34000 0x4000>;134 135 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,136 <&gcc GCC_PCIE_PHY_CFG_AHB_CLK>,137 <&gcc GCC_PCIE_CLKREF_CLK>;138 clock-names = "aux", "cfg_ahb", "ref";139 140 resets = <&gcc GCC_PCIE_PHY_BCR>,141 <&gcc GCC_PCIE_PHY_COM_BCR>,142 <&gcc GCC_PCIE_PHY_COM_NOCSR_BCR>;143 reset-names = "phy", "common", "cfg";144 145 vdda-phy-supply = <&vreg_l28a_0p925>;146 vdda-pll-supply = <&vreg_l12a_1p8>;147 148 pciephy_0: phy@1000 {149 reg = <0x1000 0x130>,150 <0x1200 0x200>,151 <0x1400 0x1dc>;152 153 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>;154 resets = <&gcc GCC_PCIE_0_PHY_BCR>;155 156 #clock-cells = <0>;157 clock-output-names = "pcie_0_pipe_clk_src";158 159 #phy-cells = <0>;160 };161 162 pciephy_1: phy@2000 {163 reg = <0x2000 0x130>,164 <0x2200 0x200>,165 <0x2400 0x1dc>;166 167 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>;168 resets = <&gcc GCC_PCIE_1_PHY_BCR>;169 170 #clock-cells = <0>;171 clock-output-names = "pcie_1_pipe_clk_src";172 173 #phy-cells = <0>;174 };175 176 pciephy_2: phy@3000 {177 reg = <0x3000 0x130>,178 <0x3200 0x200>,179 <0x3400 0x1dc>;180 181 clocks = <&gcc GCC_PCIE_2_PIPE_CLK>;182 resets = <&gcc GCC_PCIE_2_PHY_BCR>;183 184 #clock-cells = <0>;185 clock-output-names = "pcie_2_pipe_clk_src";186 187 #phy-cells = <0>;188 };189 };190