87 lines · yaml
1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)2%YAML 1.23---4$id: http://devicetree.org/schemas/phy/qcom,pcie2-phy.yaml#5$schema: http://devicetree.org/meta-schemas/core.yaml#6 7title: Qualcomm PCIe2 PHY controller8 9maintainers:10 - Vinod Koul <vkoul@kernel.org>11 12description:13 The Qualcomm PCIe2 PHY is a Synopsys based phy found in a number of Qualcomm14 platforms.15 16properties:17 compatible:18 items:19 - const: qcom,qcs404-pcie2-phy20 - const: qcom,pcie2-phy21 22 reg:23 items:24 - description: PHY register set25 26 clocks:27 items:28 - description: a clock-specifier pair for the "pipe" clock29 30 clock-output-names:31 maxItems: 132 33 "#clock-cells":34 const: 035 36 "#phy-cells":37 const: 038 39 vdda-vp-supply:40 description: low voltage regulator41 42 vdda-vph-supply:43 description: high voltage regulator44 45 resets:46 maxItems: 247 48 reset-names:49 items:50 - const: phy51 - const: pipe52 53required:54 - compatible55 - reg56 - clocks57 - clock-output-names58 - "#clock-cells"59 - "#phy-cells"60 - vdda-vp-supply61 - vdda-vph-supply62 - resets63 - reset-names64 65additionalProperties: false66 67examples:68 - |69 #include <dt-bindings/clock/qcom,gcc-qcs404.h>70 phy@7786000 {71 compatible = "qcom,qcs404-pcie2-phy", "qcom,pcie2-phy";72 reg = <0x07786000 0xb8>;73 74 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>;75 resets = <&gcc GCC_PCIEPHY_0_PHY_BCR>,76 <&gcc GCC_PCIE_0_PIPE_ARES>;77 reset-names = "phy", "pipe";78 79 vdda-vp-supply = <&vreg_l3_1p05>;80 vdda-vph-supply = <&vreg_l5_1p8>;81 82 clock-output-names = "pcie_0_pipe_clk";83 #clock-cells = <0>;84 #phy-cells = <0>;85 };86...87