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1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)2 3%YAML 1.24---5$id: http://devicetree.org/schemas/phy/qcom,qusb2-phy.yaml#6$schema: http://devicetree.org/meta-schemas/core.yaml#7 8title: Qualcomm QUSB2 phy controller9 10maintainers:11 - Wesley Cheng <quic_wcheng@quicinc.com>12 13description:14 QUSB2 controller supports LS/FS/HS usb connectivity on Qualcomm chipsets.15 16properties:17 compatible:18 oneOf:19 - items:20 - enum:21 - qcom,ipq6018-qusb2-phy22 - qcom,ipq8074-qusb2-phy23 - qcom,ipq9574-qusb2-phy24 - qcom,msm8953-qusb2-phy25 - qcom,msm8996-qusb2-phy26 - qcom,msm8998-qusb2-phy27 - qcom,qcm2290-qusb2-phy28 - qcom,sdm660-qusb2-phy29 - qcom,sm4250-qusb2-phy30 - qcom,sm6115-qusb2-phy31 - items:32 - enum:33 - qcom,sc7180-qusb2-phy34 - qcom,sdm670-qusb2-phy35 - qcom,sdm845-qusb2-phy36 - qcom,sm6350-qusb2-phy37 - const: qcom,qusb2-v2-phy38 reg:39 maxItems: 140 41 "#phy-cells":42 const: 043 44 clocks:45 minItems: 246 items:47 - description: phy config clock48 - description: 19.2 MHz ref clk49 - description: phy interface clock (Optional)50 51 clock-names:52 minItems: 253 items:54 - const: cfg_ahb55 - const: ref56 - const: iface57 58 vdd-supply:59 description:60 Phandle to 0.9V regulator supply to PHY digital circuit.61 62 vdda-pll-supply:63 description:64 Phandle to 1.8V regulator supply to PHY refclk pll block.65 66 vdda-phy-dpdm-supply:67 description:68 Phandle to 3.1V regulator supply to Dp/Dm port signals.69 70 resets:71 maxItems: 172 description:73 Phandle to reset to phy block.74 75 nvmem-cells:76 maxItems: 177 description:78 Phandle to nvmem cell that contains 'HS Tx trim'79 tuning parameter value for qusb2 phy.80 81 qcom,tcsr-syscon:82 description:83 Phandle to TCSR syscon register region.84 $ref: /schemas/types.yaml#/definitions/phandle85 86 qcom,imp-res-offset-value:87 description:88 It is a 6 bit value that specifies offset to be89 added to PHY refgen RESCODE via IMP_CTRL1 register. It is a PHY90 tuning parameter that may vary for different boards of same SOC.91 $ref: /schemas/types.yaml#/definitions/uint3292 minimum: 093 maximum: 6394 default: 095 96 qcom,bias-ctrl-value:97 description:98 It is a 6 bit value that specifies bias-ctrl-value. It is a PHY99 tuning parameter that may vary for different boards of same SOC.100 $ref: /schemas/types.yaml#/definitions/uint32101 minimum: 0102 maximum: 63103 default: 32104 105 qcom,charge-ctrl-value:106 description:107 It is a 2 bit value that specifies charge-ctrl-value. It is a PHY108 tuning parameter that may vary for different boards of same SOC.109 $ref: /schemas/types.yaml#/definitions/uint32110 minimum: 0111 maximum: 3112 default: 0113 114 qcom,hstx-trim-value:115 description:116 It is a 4 bit value that specifies tuning for HSTX117 output current.118 Possible range is - 15mA to 24mA (stepsize of 600 uA).119 See dt-bindings/phy/phy-qcom-qusb2.h for applicable values.120 $ref: /schemas/types.yaml#/definitions/uint32121 minimum: 0122 maximum: 15123 default: 3124 125 qcom,preemphasis-level:126 description:127 It is a 2 bit value that specifies pre-emphasis level.128 Possible range is 0 to 15% (stepsize of 5%).129 See dt-bindings/phy/phy-qcom-qusb2.h for applicable values.130 $ref: /schemas/types.yaml#/definitions/uint32131 minimum: 0132 maximum: 3133 default: 2134 135 qcom,preemphasis-width:136 description:137 It is a 1 bit value that specifies how long the HSTX138 pre-emphasis (specified using qcom,preemphasis-level) must be in139 effect. Duration could be half-bit of full-bit.140 See dt-bindings/phy/phy-qcom-qusb2.h for applicable values.141 $ref: /schemas/types.yaml#/definitions/uint32142 minimum: 0143 maximum: 1144 default: 0145 146 qcom,hsdisc-trim-value:147 description:148 It is a 2 bit value tuning parameter that control disconnect149 threshold and may vary for different boards of same SOC.150 $ref: /schemas/types.yaml#/definitions/uint32151 minimum: 0152 maximum: 3153 default: 0154 155required:156 - compatible157 - reg158 - "#phy-cells"159 - clocks160 - clock-names161 - vdd-supply162 - vdda-pll-supply163 - vdda-phy-dpdm-supply164 - resets165 166allOf:167 - if:168 not:169 properties:170 compatible:171 contains:172 const: qcom,qusb2-v2-phy173 then:174 properties:175 qcom,imp-res-offset-value: false176 qcom,bias-ctrl-value: false177 qcom,charge-ctrl-value: false178 qcom,hstx-trim-value: false179 qcom,preemphasis-level: false180 qcom,preemphasis-width: false181 qcom,hsdisc-trim-value: false182 183additionalProperties: false184 185examples:186 - |187 #include <dt-bindings/clock/qcom,gcc-msm8996.h>188 hsusb_phy: phy@7411000 {189 compatible = "qcom,msm8996-qusb2-phy";190 reg = <0x7411000 0x180>;191 #phy-cells = <0>;192 193 clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,194 <&gcc GCC_RX1_USB2_CLKREF_CLK>;195 clock-names = "cfg_ahb", "ref";196 197 vdd-supply = <&pm8994_l28>;198 vdda-pll-supply = <&pm8994_l12>;199 vdda-phy-dpdm-supply = <&pm8994_l24>;200 201 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;202 nvmem-cells = <&qusb2p_hstx_trim>;203 };204