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1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)2%YAML 1.23---4$id: http://devicetree.org/schemas/phy/qcom,sc8280xp-qmp-pcie-phy.yaml#5$schema: http://devicetree.org/meta-schemas/core.yaml#6 7title: Qualcomm QMP PHY controller (PCIe, SC8280XP)8 9maintainers:10 - Vinod Koul <vkoul@kernel.org>11 12description:13 The QMP PHY controller supports physical layer functionality for a number of14 controllers on Qualcomm chipsets, such as, PCIe, UFS, and USB.15 16properties:17 compatible:18 enum:19 - qcom,sa8775p-qmp-gen4x2-pcie-phy20 - qcom,sa8775p-qmp-gen4x4-pcie-phy21 - qcom,sc8180x-qmp-pcie-phy22 - qcom,sc8280xp-qmp-gen3x1-pcie-phy23 - qcom,sc8280xp-qmp-gen3x2-pcie-phy24 - qcom,sc8280xp-qmp-gen3x4-pcie-phy25 - qcom,sdm845-qhp-pcie-phy26 - qcom,sdm845-qmp-pcie-phy27 - qcom,sdx55-qmp-pcie-phy28 - qcom,sdx65-qmp-gen4x2-pcie-phy29 - qcom,sm8150-qmp-gen3x1-pcie-phy30 - qcom,sm8150-qmp-gen3x2-pcie-phy31 - qcom,sm8250-qmp-gen3x1-pcie-phy32 - qcom,sm8250-qmp-gen3x2-pcie-phy33 - qcom,sm8250-qmp-modem-pcie-phy34 - qcom,sm8350-qmp-gen3x1-pcie-phy35 - qcom,sm8450-qmp-gen3x1-pcie-phy36 - qcom,sm8450-qmp-gen4x2-pcie-phy37 - qcom,sm8550-qmp-gen3x2-pcie-phy38 - qcom,sm8550-qmp-gen4x2-pcie-phy39 - qcom,sm8650-qmp-gen3x2-pcie-phy40 - qcom,sm8650-qmp-gen4x2-pcie-phy41 - qcom,x1e80100-qmp-gen3x2-pcie-phy42 - qcom,x1e80100-qmp-gen4x2-pcie-phy43 - qcom,x1e80100-qmp-gen4x4-pcie-phy44 45 reg:46 minItems: 147 maxItems: 248 49 clocks:50 minItems: 551 maxItems: 752 53 clock-names:54 minItems: 555 items:56 - const: aux57 - const: cfg_ahb58 - const: ref59 - enum: [rchng, refgen]60 - const: pipe61 - const: pipediv262 - const: phy_aux63 64 power-domains:65 maxItems: 166 67 resets:68 minItems: 169 maxItems: 270 71 reset-names:72 minItems: 173 items:74 - const: phy75 - const: phy_nocsr76 77 vdda-phy-supply: true78 79 vdda-pll-supply: true80 81 vdda-qref-supply: true82 83 qcom,4ln-config-sel:84 description: PCIe 4-lane configuration85 $ref: /schemas/types.yaml#/definitions/phandle-array86 items:87 - items:88 - description: phandle of TCSR syscon89 - description: offset of PCIe 4-lane configuration register90 - description: offset of configuration bit for this PHY91 92 "#clock-cells": true93 94 clock-output-names:95 maxItems: 196 97 "#phy-cells":98 const: 099 100required:101 - compatible102 - reg103 - clocks104 - clock-names105 - resets106 - reset-names107 - vdda-phy-supply108 - vdda-pll-supply109 - "#clock-cells"110 - clock-output-names111 - "#phy-cells"112 113additionalProperties: false114 115allOf:116 - if:117 properties:118 compatible:119 contains:120 enum:121 - qcom,sc8280xp-qmp-gen3x4-pcie-phy122 - qcom,x1e80100-qmp-gen4x4-pcie-phy123 then:124 properties:125 reg:126 items:127 - description: port a128 - description: port b129 required:130 - qcom,4ln-config-sel131 else:132 properties:133 reg:134 maxItems: 1135 136 - if:137 properties:138 compatible:139 contains:140 enum:141 - qcom,sc8180x-qmp-pcie-phy142 - qcom,sdm845-qhp-pcie-phy143 - qcom,sdm845-qmp-pcie-phy144 - qcom,sdx55-qmp-pcie-phy145 - qcom,sm8150-qmp-gen3x1-pcie-phy146 - qcom,sm8150-qmp-gen3x2-pcie-phy147 - qcom,sm8250-qmp-gen3x1-pcie-phy148 - qcom,sm8250-qmp-gen3x2-pcie-phy149 - qcom,sm8250-qmp-modem-pcie-phy150 - qcom,sm8350-qmp-gen3x1-pcie-phy151 - qcom,sm8450-qmp-gen3x1-pcie-phy152 - qcom,sm8450-qmp-gen3x2-pcie-phy153 - qcom,sm8550-qmp-gen3x2-pcie-phy154 - qcom,sm8550-qmp-gen4x2-pcie-phy155 - qcom,sm8650-qmp-gen3x2-pcie-phy156 - qcom,sm8650-qmp-gen4x2-pcie-phy157 then:158 properties:159 clocks:160 maxItems: 5161 clock-names:162 maxItems: 5163 164 - if:165 properties:166 compatible:167 contains:168 enum:169 - qcom,sc8280xp-qmp-gen3x1-pcie-phy170 - qcom,sc8280xp-qmp-gen3x2-pcie-phy171 - qcom,sc8280xp-qmp-gen3x4-pcie-phy172 - qcom,x1e80100-qmp-gen3x2-pcie-phy173 - qcom,x1e80100-qmp-gen4x2-pcie-phy174 - qcom,x1e80100-qmp-gen4x4-pcie-phy175 then:176 properties:177 clocks:178 minItems: 6179 clock-names:180 minItems: 6181 182 - if:183 properties:184 compatible:185 contains:186 enum:187 - qcom,sa8775p-qmp-gen4x2-pcie-phy188 - qcom,sa8775p-qmp-gen4x4-pcie-phy189 then:190 properties:191 clocks:192 minItems: 7193 clock-names:194 minItems: 7195 196 - if:197 properties:198 compatible:199 contains:200 enum:201 - qcom,sm8550-qmp-gen4x2-pcie-phy202 - qcom,sm8650-qmp-gen4x2-pcie-phy203 - qcom,x1e80100-qmp-gen4x2-pcie-phy204 - qcom,x1e80100-qmp-gen4x4-pcie-phy205 then:206 properties:207 resets:208 minItems: 2209 reset-names:210 minItems: 2211 else:212 properties:213 resets:214 maxItems: 1215 reset-names:216 maxItems: 1217 218 - if:219 properties:220 compatible:221 contains:222 enum:223 - qcom,sm8450-qmp-gen4x2-pcie-phy224 - qcom,sm8550-qmp-gen4x2-pcie-phy225 - qcom,sm8650-qmp-gen4x2-pcie-phy226 then:227 properties:228 "#clock-cells":229 const: 1230 else:231 properties:232 "#clock-cells":233 const: 0234 235examples:236 - |237 #include <dt-bindings/clock/qcom,gcc-sc8280xp.h>238 239 pcie2b_phy: phy@1c18000 {240 compatible = "qcom,sc8280xp-qmp-gen3x2-pcie-phy";241 reg = <0x01c18000 0x2000>;242 243 clocks = <&gcc GCC_PCIE_2B_AUX_CLK>,244 <&gcc GCC_PCIE_2B_CFG_AHB_CLK>,245 <&gcc GCC_PCIE_2A2B_CLKREF_CLK>,246 <&gcc GCC_PCIE2B_PHY_RCHNG_CLK>,247 <&gcc GCC_PCIE_2B_PIPE_CLK>,248 <&gcc GCC_PCIE_2B_PIPEDIV2_CLK>;249 clock-names = "aux", "cfg_ahb", "ref", "rchng",250 "pipe", "pipediv2";251 252 power-domains = <&gcc PCIE_2B_GDSC>;253 254 resets = <&gcc GCC_PCIE_2B_PHY_BCR>;255 reset-names = "phy";256 257 vdda-phy-supply = <&vreg_l6d>;258 vdda-pll-supply = <&vreg_l4d>;259 260 #clock-cells = <0>;261 clock-output-names = "pcie_2b_pipe_clk";262 263 #phy-cells = <0>;264 };265 266 pcie2a_phy: phy@1c24000 {267 compatible = "qcom,sc8280xp-qmp-gen3x4-pcie-phy";268 reg = <0x01c24000 0x2000>, <0x01c26000 0x2000>;269 270 clocks = <&gcc GCC_PCIE_2A_AUX_CLK>,271 <&gcc GCC_PCIE_2A_CFG_AHB_CLK>,272 <&gcc GCC_PCIE_2A2B_CLKREF_CLK>,273 <&gcc GCC_PCIE2A_PHY_RCHNG_CLK>,274 <&gcc GCC_PCIE_2A_PIPE_CLK>,275 <&gcc GCC_PCIE_2A_PIPEDIV2_CLK>;276 clock-names = "aux", "cfg_ahb", "ref", "rchng",277 "pipe", "pipediv2";278 279 power-domains = <&gcc PCIE_2A_GDSC>;280 281 resets = <&gcc GCC_PCIE_2A_PHY_BCR>;282 reset-names = "phy";283 284 vdda-phy-supply = <&vreg_l6d>;285 vdda-pll-supply = <&vreg_l4d>;286 287 qcom,4ln-config-sel = <&tcsr 0xa044 0>;288 289 #clock-cells = <0>;290 clock-output-names = "pcie_2a_pipe_clk";291 292 #phy-cells = <0>;293 };294