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1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)2%YAML 1.23---4$id: http://devicetree.org/schemas/phy/qcom,sc8280xp-qmp-ufs-phy.yaml#5$schema: http://devicetree.org/meta-schemas/core.yaml#6 7title: Qualcomm QMP PHY controller (UFS, SC8280XP)8 9maintainers:10 - Vinod Koul <vkoul@kernel.org>11 12description:13 The QMP PHY controller supports physical layer functionality for a number of14 controllers on Qualcomm chipsets, such as, PCIe, UFS, and USB.15 16properties:17 compatible:18 enum:19 - qcom,msm8996-qmp-ufs-phy20 - qcom,msm8998-qmp-ufs-phy21 - qcom,sa8775p-qmp-ufs-phy22 - qcom,sc7180-qmp-ufs-phy23 - qcom,sc7280-qmp-ufs-phy24 - qcom,sc8180x-qmp-ufs-phy25 - qcom,sc8280xp-qmp-ufs-phy26 - qcom,sdm845-qmp-ufs-phy27 - qcom,sm6115-qmp-ufs-phy28 - qcom,sm6125-qmp-ufs-phy29 - qcom,sm6350-qmp-ufs-phy30 - qcom,sm7150-qmp-ufs-phy31 - qcom,sm8150-qmp-ufs-phy32 - qcom,sm8250-qmp-ufs-phy33 - qcom,sm8350-qmp-ufs-phy34 - qcom,sm8450-qmp-ufs-phy35 - qcom,sm8475-qmp-ufs-phy36 - qcom,sm8550-qmp-ufs-phy37 - qcom,sm8650-qmp-ufs-phy38 39 reg:40 maxItems: 141 42 clocks:43 minItems: 244 maxItems: 345 46 clock-names:47 minItems: 248 maxItems: 349 50 power-domains:51 maxItems: 152 53 resets:54 maxItems: 155 56 reset-names:57 items:58 - const: ufsphy59 60 vdda-phy-supply: true61 62 vdda-pll-supply: true63 64 "#clock-cells":65 const: 166 67 "#phy-cells":68 const: 069 70required:71 - compatible72 - reg73 - clocks74 - clock-names75 - resets76 - reset-names77 - vdda-phy-supply78 - vdda-pll-supply79 - "#phy-cells"80 81allOf:82 - if:83 properties:84 compatible:85 contains:86 enum:87 - qcom,msm8998-qmp-ufs-phy88 - qcom,sa8775p-qmp-ufs-phy89 - qcom,sc7180-qmp-ufs-phy90 - qcom,sc7280-qmp-ufs-phy91 - qcom,sc8180x-qmp-ufs-phy92 - qcom,sc8280xp-qmp-ufs-phy93 - qcom,sdm845-qmp-ufs-phy94 - qcom,sm6115-qmp-ufs-phy95 - qcom,sm6125-qmp-ufs-phy96 - qcom,sm6350-qmp-ufs-phy97 - qcom,sm7150-qmp-ufs-phy98 - qcom,sm8150-qmp-ufs-phy99 - qcom,sm8250-qmp-ufs-phy100 - qcom,sm8350-qmp-ufs-phy101 - qcom,sm8450-qmp-ufs-phy102 - qcom,sm8475-qmp-ufs-phy103 - qcom,sm8550-qmp-ufs-phy104 - qcom,sm8650-qmp-ufs-phy105 then:106 properties:107 clocks:108 minItems: 3109 maxItems: 3110 clock-names:111 items:112 - const: ref113 - const: ref_aux114 - const: qref115 116 - if:117 properties:118 compatible:119 contains:120 enum:121 - qcom,msm8996-qmp-ufs-phy122 then:123 properties:124 clocks:125 minItems: 2126 maxItems: 2127 clock-names:128 items:129 - const: ref130 - const: qref131 132 - if:133 properties:134 compatible:135 contains:136 enum:137 - qcom,msm8996-qmp-ufs-phy138 - qcom,msm8998-qmp-ufs-phy139 then:140 properties:141 power-domains:142 false143 else:144 required:145 - power-domains146 147additionalProperties: false148 149examples:150 - |151 #include <dt-bindings/clock/qcom,gcc-sc8280xp.h>152 #include <dt-bindings/clock/qcom,rpmh.h>153 154 ufs_mem_phy: phy@1d87000 {155 compatible = "qcom,sc8280xp-qmp-ufs-phy";156 reg = <0x01d87000 0x1000>;157 158 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_UFS_PHY_PHY_AUX_CLK>,159 <&gcc GCC_UFS_REF_CLKREF_CLK>;160 161 clock-names = "ref", "ref_aux", "qref";162 163 power-domains = <&gcc UFS_PHY_GDSC>;164 165 resets = <&ufs_mem_hc 0>;166 reset-names = "ufsphy";167 168 vdda-phy-supply = <&vreg_l6b>;169 vdda-pll-supply = <&vreg_l3b>;170 171 #phy-cells = <0>;172 };173