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1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)2%YAML 1.23---4$id: http://devicetree.org/schemas/phy/qcom,usb-hs-28nm.yaml#5$schema: http://devicetree.org/meta-schemas/core.yaml#6 7title: Qualcomm Synopsys DesignWare Core 28nm High-Speed PHY8 9maintainers:10 - Bryan O'Donoghue <bryan.odonoghue@linaro.org>11 12description: |13 Qualcomm Low-Speed, Full-Speed, Hi-Speed 28nm USB PHY14 15properties:16 compatible:17 enum:18 - qcom,usb-hs-28nm-femtophy19 20 reg:21 maxItems: 122 23 "#phy-cells":24 const: 025 26 clocks:27 items:28 - description: rpmcc ref clock29 - description: PHY AHB clock30 - description: Rentention clock31 32 clock-names:33 items:34 - const: ref35 - const: ahb36 - const: sleep37 38 resets:39 items:40 - description: PHY core reset41 - description: POR reset42 43 reset-names:44 items:45 - const: phy46 - const: por47 48 vdd-supply:49 description: phandle to the regulator VDD supply node.50 51 vdda1p8-supply:52 description: phandle to the regulator 1.8V supply node.53 54 vdda3p3-supply:55 description: phandle to the regulator 3.3V supply node.56 57required:58 - compatible59 - reg60 - "#phy-cells"61 - clocks62 - clock-names63 - resets64 - reset-names65 - vdd-supply66 - vdda1p8-supply67 - vdda3p3-supply68 69additionalProperties: false70 71examples:72 - |73 #include <dt-bindings/clock/qcom,gcc-qcs404.h>74 #include <dt-bindings/clock/qcom,rpmcc.h>75 usb2_phy_prim: phy@7a000 {76 compatible = "qcom,usb-hs-28nm-femtophy";77 reg = <0x0007a000 0x200>;78 #phy-cells = <0>;79 clocks = <&rpmcc RPM_SMD_LN_BB_CLK>,80 <&gcc GCC_USB_HS_PHY_CFG_AHB_CLK>,81 <&gcc GCC_USB2A_PHY_SLEEP_CLK>;82 clock-names = "ref", "ahb", "sleep";83 resets = <&gcc GCC_USB_HS_PHY_CFG_AHB_BCR>,84 <&gcc GCC_USB2A_PHY_BCR>;85 reset-names = "phy", "por";86 vdd-supply = <&vreg_l4_1p2>;87 vdda1p8-supply = <&vreg_l5_1p8>;88 vdda3p3-supply = <&vreg_l12_3p3>;89 };90...91