114 lines · yaml
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)2%YAML 1.23---4$id: http://devicetree.org/schemas/phy/rockchip,pcie3-phy.yaml#5$schema: http://devicetree.org/meta-schemas/core.yaml#6 7title: Rockchip PCIe v3 phy8 9maintainers:10 - Heiko Stuebner <heiko@sntech.de>11 12properties:13 compatible:14 enum:15 - rockchip,rk3568-pcie3-phy16 - rockchip,rk3588-pcie3-phy17 18 reg:19 maxItems: 120 21 clocks:22 minItems: 123 maxItems: 324 25 clock-names:26 minItems: 127 maxItems: 328 29 data-lanes:30 description: which lanes (by position) should be mapped to which31 controller (value). 0 means lane disabled, higher value means used.32 (controller-number +1 )33 $ref: /schemas/types.yaml#/definitions/uint32-array34 minItems: 235 maxItems: 1636 items:37 minimum: 038 maximum: 1639 40 "#phy-cells":41 const: 042 43 resets:44 maxItems: 145 46 reset-names:47 const: phy48 49 rockchip,phy-grf:50 $ref: /schemas/types.yaml#/definitions/phandle51 description: phandle to the syscon managing the phy "general register files"52 53 rockchip,pipe-grf:54 $ref: /schemas/types.yaml#/definitions/phandle55 description: phandle to the syscon managing the pipe "general register files"56 57 rockchip,rx-common-refclk-mode:58 description: which lanes (by position) should be configured to run in59 RX common reference clock mode. 0 means disabled, 1 means enabled.60 $ref: /schemas/types.yaml#/definitions/uint32-array61 minItems: 162 maxItems: 1663 items:64 minimum: 065 maximum: 166 67required:68 - compatible69 - reg70 - rockchip,phy-grf71 - "#phy-cells"72 73allOf:74 - if:75 properties:76 compatible:77 enum:78 - rockchip,rk3588-pcie3-phy79 then:80 properties:81 clocks:82 maxItems: 183 clock-names:84 items:85 - const: pclk86 else:87 properties:88 clocks:89 minItems: 390 91 clock-names:92 items:93 - const: refclk_m94 - const: refclk_n95 - const: pclk96 97additionalProperties: false98 99examples:100 - |101 #include <dt-bindings/clock/rk3568-cru.h>102 pcie30phy: phy@fe8c0000 {103 compatible = "rockchip,rk3568-pcie3-phy";104 reg = <0xfe8c0000 0x20000>;105 #phy-cells = <0>;106 clocks = <&pmucru CLK_PCIE30PHY_REF_M>,107 <&pmucru CLK_PCIE30PHY_REF_N>,108 <&cru PCLK_PCIE30PHY>;109 clock-names = "refclk_m", "refclk_n", "pclk";110 resets = <&cru SRST_PCIE30PHY>;111 reset-names = "phy";112 rockchip,phy-grf = <&pcie30_phy_grf>;113 };114