73 lines · yaml
1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)2%YAML 1.23---4$id: http://devicetree.org/schemas/phy/rockchip,px30-dsi-dphy.yaml#5$schema: http://devicetree.org/meta-schemas/core.yaml#6 7title: Rockchip MIPI DPHY with additional LVDS/TTL modes8 9maintainers:10 - Heiko Stuebner <heiko@sntech.de>11 12properties:13 "#phy-cells":14 const: 015 16 compatible:17 enum:18 - rockchip,px30-dsi-dphy19 - rockchip,rk3128-dsi-dphy20 - rockchip,rk3368-dsi-dphy21 - rockchip,rk3568-dsi-dphy22 - rockchip,rv1126-dsi-dphy23 24 reg:25 maxItems: 126 27 clocks:28 items:29 - description: PLL reference clock30 - description: Module clock31 32 clock-names:33 items:34 - const: ref35 - const: pclk36 37 power-domains:38 maxItems: 139 description: phandle to the associated power domain40 41 resets:42 items:43 - description: exclusive PHY reset line44 45 reset-names:46 items:47 - const: apb48 49required:50 - "#phy-cells"51 - compatible52 - reg53 - clocks54 - clock-names55 - resets56 - reset-names57 58additionalProperties: false59 60examples:61 - |62 dsi_dphy: phy@ff2e0000 {63 compatible = "rockchip,px30-dsi-dphy";64 reg = <0xff2e0000 0x10000>;65 clocks = <&pmucru 13>, <&cru 12>;66 clock-names = "ref", "pclk";67 resets = <&cru 12>;68 reset-names = "apb";69 #phy-cells = <0>;70 };71 72...73