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1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)2%YAML 1.23---4$id: http://devicetree.org/schemas/phy/rockchip,rk3588-hdptx-phy.yaml#5$schema: http://devicetree.org/meta-schemas/core.yaml#6 7title: Rockchip SoC HDMI/eDP Transmitter Combo PHY8 9maintainers:10 - Cristian Ciocaltea <cristian.ciocaltea@collabora.com>11 12properties:13 compatible:14 enum:15 - rockchip,rk3588-hdptx-phy16 17 reg:18 maxItems: 119 20 clocks:21 items:22 - description: Reference clock23 - description: APB clock24 25 clock-names:26 items:27 - const: ref28 - const: apb29 30 "#clock-cells":31 const: 032 33 "#phy-cells":34 const: 035 36 resets:37 items:38 - description: PHY reset line39 - description: APB reset line40 - description: INIT reset line41 - description: CMN reset line42 - description: LANE reset line43 - description: ROPLL reset line44 - description: LCPLL reset line45 46 reset-names:47 items:48 - const: phy49 - const: apb50 - const: init51 - const: cmn52 - const: lane53 - const: ropll54 - const: lcpll55 56 rockchip,grf:57 $ref: /schemas/types.yaml#/definitions/phandle58 description: Some PHY related data is accessed through GRF regs.59 60required:61 - compatible62 - reg63 - clocks64 - clock-names65 - "#phy-cells"66 - resets67 - reset-names68 - rockchip,grf69 70additionalProperties: false71 72examples:73 - |74 #include <dt-bindings/clock/rockchip,rk3588-cru.h>75 #include <dt-bindings/reset/rockchip,rk3588-cru.h>76 77 soc {78 #address-cells = <2>;79 #size-cells = <2>;80 81 phy@fed60000 {82 compatible = "rockchip,rk3588-hdptx-phy";83 reg = <0x0 0xfed60000 0x0 0x2000>;84 clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>, <&cru PCLK_HDPTX0>;85 clock-names = "ref", "apb";86 #phy-cells = <0>;87 resets = <&cru SRST_HDPTX0>, <&cru SRST_P_HDPTX0>,88 <&cru SRST_HDPTX0_INIT>, <&cru SRST_HDPTX0_CMN>,89 <&cru SRST_HDPTX0_LANE>, <&cru SRST_HDPTX0_ROPLL>,90 <&cru SRST_HDPTX0_LCPLL>;91 reset-names = "phy", "apb", "init", "cmn", "lane", "ropll", "lcpll";92 rockchip,grf = <&hdptxphy_grf>;93 };94 };95