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1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)2%YAML 1.23---4$id: http://devicetree.org/schemas/phy/rockchip-inno-csi-dphy.yaml#5$schema: http://devicetree.org/meta-schemas/core.yaml#6 7title: Rockchip SoC MIPI RX0 D-PHY8 9maintainers:10 - Heiko Stuebner <heiko@sntech.de>11 12description: |13 The Rockchip SoC has a MIPI CSI D-PHY based on an Innosilicon IP which14 connects to the ISP1 (Image Signal Processing unit v1.0) for CSI cameras.15 16properties:17 compatible:18 enum:19 - rockchip,px30-csi-dphy20 - rockchip,rk1808-csi-dphy21 - rockchip,rk3326-csi-dphy22 - rockchip,rk3368-csi-dphy23 - rockchip,rk3568-csi-dphy24 25 reg:26 maxItems: 127 28 clocks:29 maxItems: 130 31 clock-names:32 const: pclk33 34 '#phy-cells':35 const: 036 37 power-domains:38 description: Video in/out power domain.39 maxItems: 140 41 resets:42 items:43 - description: exclusive PHY reset line44 45 reset-names:46 items:47 - const: apb48 49 rockchip,grf:50 $ref: /schemas/types.yaml#/definitions/phandle51 description:52 Some additional phy settings are access through GRF regs.53 54required:55 - compatible56 - reg57 - clocks58 - clock-names59 - '#phy-cells'60 - power-domains61 - resets62 - reset-names63 - rockchip,grf64 65additionalProperties: false66 67examples:68 - |69 70 csi_dphy: phy@ff2f0000 {71 compatible = "rockchip,px30-csi-dphy";72 reg = <0xff2f0000 0x4000>;73 clocks = <&cru 1>;74 clock-names = "pclk";75 #phy-cells = <0>;76 power-domains = <&power 1>;77 resets = <&cru 1>;78 reset-names = "apb";79 rockchip,grf = <&grf>;80 };81