114 lines · yaml
1# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause2%YAML 1.23---4$id: http://devicetree.org/schemas/phy/samsung,ufs-phy.yaml#5$schema: http://devicetree.org/meta-schemas/core.yaml#6 7title: Samsung SoC series UFS PHY8 9maintainers:10 - Alim Akhtar <alim.akhtar@samsung.com>11 12properties:13 "#phy-cells":14 const: 015 16 compatible:17 enum:18 - google,gs101-ufs-phy19 - samsung,exynos7-ufs-phy20 - samsung,exynosautov9-ufs-phy21 - tesla,fsd-ufs-phy22 23 reg:24 maxItems: 125 26 reg-names:27 items:28 - const: phy-pma29 30 clocks:31 minItems: 132 maxItems: 433 34 clock-names:35 minItems: 136 maxItems: 437 38 samsung,pmu-syscon:39 $ref: /schemas/types.yaml#/definitions/phandle-array40 maxItems: 141 items:42 minItems: 143 items:44 - description: phandle for PMU system controller interface, used to45 control pmu registers bits for ufs m-phy46 - description: offset of the pmu control register47 description:48 It can be phandle/offset pair. The second cell which can represent an49 offset is optional.50 51required:52 - "#phy-cells"53 - compatible54 - reg55 - reg-names56 - clocks57 - clock-names58 - samsung,pmu-syscon59 60allOf:61 - if:62 properties:63 compatible:64 contains:65 const: samsung,exynos7-ufs-phy66 67 then:68 properties:69 clocks:70 items:71 - description: PLL reference clock72 - description: symbol clock for input symbol (rx0-ch0 symbol clock)73 - description: symbol clock for input symbol (rx1-ch1 symbol clock)74 - description: symbol clock for output symbol (tx0 symbol clock)75 76 clock-names:77 items:78 - const: ref_clk79 - const: rx1_symbol_clk80 - const: rx0_symbol_clk81 - const: tx0_symbol_clk82 83 else:84 properties:85 clocks:86 items:87 - description: PLL reference clock88 89 clock-names:90 items:91 - const: ref_clk92 93additionalProperties: false94 95examples:96 - |97 #include <dt-bindings/clock/exynos7-clk.h>98 99 ufs_phy: ufs-phy@15571800 {100 compatible = "samsung,exynos7-ufs-phy";101 reg = <0x15571800 0x240>;102 reg-names = "phy-pma";103 samsung,pmu-syscon = <&pmu_system_controller>;104 #phy-cells = <0>;105 clocks = <&clock_fsys1 SCLK_COMBO_PHY_EMBEDDED_26M>,106 <&clock_fsys1 PHYCLK_UFS20_RX1_SYMBOL_USER>,107 <&clock_fsys1 PHYCLK_UFS20_RX0_SYMBOL_USER>,108 <&clock_fsys1 PHYCLK_UFS20_TX0_SYMBOL_USER>;109 clock-names = "ref_clk", "rx1_symbol_clk",110 "rx0_symbol_clk", "tx0_symbol_clk";111 112 };113...114