106 lines · yaml
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)2%YAML 1.23---4$id: http://devicetree.org/schemas/phy/socionext,uniphier-pcie-phy.yaml#5$schema: http://devicetree.org/meta-schemas/core.yaml#6 7title: Socionext UniPhier PCIe PHY8 9description: |10 This describes the devicetree bindings for PHY interface built into11 PCIe controller implemented on Socionext UniPhier SoCs.12 13maintainers:14 - Kunihiko Hayashi <hayashi.kunihiko@socionext.com>15 16properties:17 compatible:18 enum:19 - socionext,uniphier-pro5-pcie-phy20 - socionext,uniphier-ld20-pcie-phy21 - socionext,uniphier-pxs3-pcie-phy22 - socionext,uniphier-nx1-pcie-phy23 24 reg:25 maxItems: 126 27 "#phy-cells":28 const: 029 30 clocks:31 minItems: 132 maxItems: 233 34 clock-names:35 minItems: 136 maxItems: 237 38 resets:39 minItems: 140 maxItems: 241 42 reset-names:43 minItems: 144 maxItems: 245 46 socionext,syscon:47 $ref: /schemas/types.yaml#/definitions/phandle48 description: A phandle to system control to set configurations for phy49 50allOf:51 - if:52 properties:53 compatible:54 contains:55 const: socionext,uniphier-pro5-pcie-phy56 then:57 properties:58 clocks:59 minItems: 260 maxItems: 261 clock-names:62 items:63 - const: gio64 - const: link65 resets:66 minItems: 267 maxItems: 268 reset-names:69 items:70 - const: gio71 - const: link72 else:73 properties:74 clocks:75 maxItems: 176 clock-names:77 const: link78 resets:79 maxItems: 180 reset-names:81 const: link82 83required:84 - compatible85 - reg86 - "#phy-cells"87 - clocks88 - clock-names89 - resets90 - reset-names91 92additionalProperties: false93 94examples:95 - |96 pcie_phy: phy@66038000 {97 compatible = "socionext,uniphier-ld20-pcie-phy";98 reg = <0x66038000 0x4000>;99 #phy-cells = <0>;100 clock-names = "link";101 clocks = <&sys_clk 24>;102 reset-names = "link";103 resets = <&sys_rst 24>;104 socionext,syscon = <&soc_glue>;105 };106