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1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)2%YAML 1.23---4$id: http://devicetree.org/schemas/phy/socionext,uniphier-usb3hs-phy.yaml#5$schema: http://devicetree.org/meta-schemas/core.yaml#6 7title: Socionext UniPhier USB3 High-Speed (HS) PHY8 9description: |10 This describes the devicetree bindings for PHY interfaces built into11 USB3 controller implemented on Socionext UniPhier SoCs.12 Although the controller includes High-Speed PHY and Super-Speed PHY,13 this describes about High-Speed PHY.14 15maintainers:16 - Kunihiko Hayashi <hayashi.kunihiko@socionext.com>17 18properties:19 compatible:20 enum:21 - socionext,uniphier-pro5-usb3-hsphy22 - socionext,uniphier-pxs2-usb3-hsphy23 - socionext,uniphier-ld20-usb3-hsphy24 - socionext,uniphier-pxs3-usb3-hsphy25 - socionext,uniphier-nx1-usb3-hsphy26 27 reg:28 maxItems: 129 30 "#phy-cells":31 const: 032 33 clocks:34 minItems: 235 maxItems: 336 37 clock-names:38 minItems: 239 maxItems: 340 41 resets:42 maxItems: 243 44 reset-names:45 maxItems: 246 47 vbus-supply:48 description: A phandle to the regulator for USB VBUS49 50 nvmem-cells:51 maxItems: 352 description:53 Phandles to nvmem cell that contains the trimming data.54 Available only for HS-PHY implemented on LD20 and PXs3, and55 if unspecified, default value is used.56 57 nvmem-cell-names:58 items:59 - const: rterm60 - const: sel_t61 - const: hs_i62 description:63 Should be the following names, which correspond to each nvmem-cells.64 All of the 3 parameters associated with the above names are65 required for each port, if any one is omitted, the trimming data66 of the port will not be set at all.67 68allOf:69 - if:70 properties:71 compatible:72 contains:73 const: socionext,uniphier-pro5-usb3-hsphy74 then:75 properties:76 clocks:77 minItems: 278 maxItems: 279 clock-names:80 items:81 - const: gio82 - const: link83 resets:84 minItems: 285 maxItems: 286 reset-names:87 items:88 - const: gio89 - const: link90 - if:91 properties:92 compatible:93 contains:94 enum:95 - socionext,uniphier-pxs2-usb3-hsphy96 - socionext,uniphier-ld20-usb3-hsphy97 then:98 properties:99 clocks:100 minItems: 2101 maxItems: 2102 clock-names:103 items:104 - const: link105 - const: phy106 resets:107 minItems: 2108 maxItems: 2109 reset-names:110 items:111 - const: link112 - const: phy113 - if:114 properties:115 compatible:116 contains:117 enum:118 - socionext,uniphier-pxs3-usb3-hsphy119 - socionext,uniphier-nx1-usb3-hsphy120 then:121 properties:122 clocks:123 minItems: 2124 maxItems: 3125 clock-names:126 minItems: 2127 items:128 - const: link129 - const: phy130 - const: phy-ext131 resets:132 minItems: 2133 maxItems: 2134 reset-names:135 items:136 - const: link137 - const: phy138 139required:140 - compatible141 - reg142 - "#phy-cells"143 - clocks144 - clock-names145 - resets146 - reset-names147 148additionalProperties: false149 150examples:151 - |152 usb_hsphy0: phy@200 {153 compatible = "socionext,uniphier-ld20-usb3-hsphy";154 reg = <0x200 0x10>;155 #phy-cells = <0>;156 clock-names = "link", "phy";157 clocks = <&sys_clk 14>, <&sys_clk 16>;158 reset-names = "link", "phy";159 resets = <&sys_rst 14>, <&sys_rst 16>;160 vbus-supply = <&usb_vbus0>;161 nvmem-cell-names = "rterm", "sel_t", "hs_i";162 nvmem-cells = <&usb_rterm0>, <&usb_sel_t0>, <&usb_hs_i0>;163 };164