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1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)2%YAML 1.23---4$id: http://devicetree.org/schemas/phy/socionext,uniphier-usb3ss-phy.yaml#5$schema: http://devicetree.org/meta-schemas/core.yaml#6 7title: Socionext UniPhier USB3 Super-Speed (SS) PHY8 9description: |10 This describes the devicetree bindings for PHY interfaces built into11 USB3 controller implemented on Socionext UniPhier SoCs.12 Although the controller includes High-Speed PHY and Super-Speed PHY,13 this describes about Super-Speed PHY.14 15maintainers:16 - Kunihiko Hayashi <hayashi.kunihiko@socionext.com>17 18properties:19 compatible:20 enum:21 - socionext,uniphier-pro4-usb3-ssphy22 - socionext,uniphier-pro5-usb3-ssphy23 - socionext,uniphier-pxs2-usb3-ssphy24 - socionext,uniphier-ld20-usb3-ssphy25 - socionext,uniphier-pxs3-usb3-ssphy26 - socionext,uniphier-nx1-usb3-ssphy27 28 reg:29 maxItems: 130 31 "#phy-cells":32 const: 033 34 clocks:35 minItems: 236 maxItems: 337 38 clock-names:39 minItems: 240 maxItems: 341 42 resets:43 maxItems: 244 45 reset-names:46 maxItems: 247 48 vbus-supply:49 description: A phandle to the regulator for USB VBUS, only for USB host50 51allOf:52 - if:53 properties:54 compatible:55 contains:56 enum:57 - socionext,uniphier-pro4-usb3-ssphy58 - socionext,uniphier-pro5-usb3-ssphy59 then:60 properties:61 clocks:62 minItems: 263 maxItems: 264 clock-names:65 items:66 - const: gio67 - const: link68 resets:69 minItems: 270 maxItems: 271 reset-names:72 items:73 - const: gio74 - const: link75 - if:76 properties:77 compatible:78 contains:79 enum:80 - socionext,uniphier-pxs2-usb3-ssphy81 - socionext,uniphier-ld20-usb3-ssphy82 then:83 properties:84 clocks:85 minItems: 286 maxItems: 287 clock-names:88 items:89 - const: link90 - const: phy91 resets:92 minItems: 293 maxItems: 294 reset-names:95 items:96 - const: link97 - const: phy98 - if:99 properties:100 compatible:101 contains:102 enum:103 - socionext,uniphier-pxs3-usb3-ssphy104 - socionext,uniphier-nx1-usb3-ssphy105 then:106 properties:107 clocks:108 minItems: 2109 maxItems: 3110 clock-names:111 minItems: 2112 items:113 - const: link114 - const: phy115 - const: phy-ext116 resets:117 minItems: 2118 maxItems: 2119 reset-names:120 items:121 - const: link122 - const: phy123 124required:125 - compatible126 - reg127 - "#phy-cells"128 - clocks129 - clock-names130 - resets131 - reset-names132 133additionalProperties: false134 135examples:136 - |137 usb_ssphy0: phy@300 {138 compatible = "socionext,uniphier-ld20-usb3-ssphy";139 reg = <0x300 0x10>;140 #phy-cells = <0>;141 clock-names = "link", "phy";142 clocks = <&sys_clk 14>, <&sys_clk 16>;143 reset-names = "link", "phy";144 resets = <&sys_rst 14>, <&sys_rst 16>;145 vbus-supply = <&usb_vbus0>;146 };147