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1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)2%YAML 1.23---4$id: http://devicetree.org/schemas/phy/starfive,jh7110-pcie-phy.yaml#5$schema: http://devicetree.org/meta-schemas/core.yaml#6 7title: StarFive JH7110 PCIe 2.0 PHY8 9maintainers:10 - Minda Chen <minda.chen@starfivetech.com>11 12properties:13 compatible:14 const: starfive,jh7110-pcie-phy15 16 reg:17 maxItems: 118 19 "#phy-cells":20 const: 021 22 starfive,sys-syscon:23 $ref: /schemas/types.yaml#/definitions/phandle-array24 items:25 - items:26 - description: phandle to System Register Controller sys_syscon node.27 - description: PHY connect offset of SYS_SYSCONSAIF__SYSCFG register for USB PHY.28 description:29 The phandle to System Register Controller syscon node and the PHY connect offset30 of SYS_SYSCONSAIF__SYSCFG register. Connect PHY to USB3 controller.31 32 starfive,stg-syscon:33 $ref: /schemas/types.yaml#/definitions/phandle-array34 items:35 - items:36 - description: phandle to System Register Controller stg_syscon node.37 - description: PHY mode offset of STG_SYSCONSAIF__SYSCFG register.38 - description: PHY enable for USB offset of STG_SYSCONSAIF__SYSCFG register.39 description:40 The phandle to System Register Controller syscon node and the offset41 of STG_SYSCONSAIF__SYSCFG register for PCIe PHY. Total 2 regsisters offset.42 43required:44 - compatible45 - reg46 - "#phy-cells"47 48additionalProperties: false49 50examples:51 - |52 phy@10210000 {53 compatible = "starfive,jh7110-pcie-phy";54 reg = <0x10210000 0x10000>;55 #phy-cells = <0>;56 starfive,sys-syscon = <&sys_syscon 0x18>;57 starfive,stg-syscon = <&stg_syscon 0x148 0x1f4>;58 };59