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1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)2# Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/3%YAML 1.24---5$id: http://devicetree.org/schemas/phy/ti,phy-gmii-sel.yaml#6$schema: http://devicetree.org/meta-schemas/core.yaml#7 8title: CPSW Port's Interface Mode Selection PHY9 10maintainers:11 - Kishon Vijay Abraham I <kishon@ti.com>12 13description: |14 TI am335x/am437x/dra7(am5)/dm814x CPSW3G Ethernet Subsystem supports15 two 10/100/1000 Ethernet ports with selectable G/MII, RMII, and RGMII interfaces.16 The interface mode is selected by configuring the MII mode selection register(s)17 (GMII_SEL) in the System Control Module chapter (SCM). GMII_SEL register(s) and18 bit fields placement in SCM are different between SoCs while fields meaning19 is the same.20 +--------------+21 +-------------------------------+ |SCM |22 | CPSW | | +---------+ |23 | +--------------------------------+gmii_sel | |24 | | | | +---------+ |25 | +----v---+ +--------+ | +--------------+26 | |Port 1..<--+-->GMII/MII<------->27 | | | | | | |28 | +--------+ | +--------+ |29 | | |30 | | +--------+ |31 | | | RMII <------->32 | +--> | |33 | | +--------+ |34 | | |35 | | +--------+ |36 | | | RGMII <------->37 | +--> | |38 | +--------+ |39 +-------------------------------+40 41 CPSW Port's Interface Mode Selection PHY describes MII interface mode between42 CPSW Port and Ethernet PHY which depends on Eth PHY and board configuration.43 |44 CPSW Port's Interface Mode Selection PHY device should defined as child device45 of SCM node (scm_conf) and can be attached to each CPSW port node using standard46 PHY bindings.47 48properties:49 compatible:50 enum:51 - ti,am3352-phy-gmii-sel52 - ti,dra7xx-phy-gmii-sel53 - ti,am43xx-phy-gmii-sel54 - ti,dm814-phy-gmii-sel55 - ti,am654-phy-gmii-sel56 - ti,j7200-cpsw5g-phy-gmii-sel57 - ti,j721e-cpsw9g-phy-gmii-sel58 - ti,j784s4-cpsw9g-phy-gmii-sel59 60 reg:61 maxItems: 162 63 '#phy-cells': true64 65 ti,qsgmii-main-ports:66 $ref: /schemas/types.yaml#/definitions/uint32-array67 description: |68 Required only for QSGMII mode. Array to select the port/s for QSGMII69 main mode. The size of the array corresponds to the number of QSGMII70 interfaces and thus, the number of distinct QSGMII main ports,71 supported by the device. If the device supports two QSGMII interfaces72 but only one QSGMII interface is desired, repeat the QSGMII main port73 value corresponding to the QSGMII interface in the array.74 minItems: 175 maxItems: 276 items:77 minimum: 178 maximum: 879 80allOf:81 - if:82 properties:83 compatible:84 contains:85 enum:86 - ti,dra7xx-phy-gmii-sel87 - ti,dm814-phy-gmii-sel88 - ti,am654-phy-gmii-sel89 - ti,j7200-cpsw5g-phy-gmii-sel90 - ti,j721e-cpsw9g-phy-gmii-sel91 - ti,j784s4-cpsw9g-phy-gmii-sel92 then:93 properties:94 '#phy-cells':95 const: 196 description: CPSW port number (starting from 1)97 98 - if:99 properties:100 compatible:101 contains:102 enum:103 - ti,j7200-cpsw5g-phy-gmii-sel104 then:105 properties:106 ti,qsgmii-main-ports:107 maxItems: 1108 items:109 minimum: 1110 maximum: 4111 112 - if:113 properties:114 compatible:115 contains:116 enum:117 - ti,j721e-cpsw9g-phy-gmii-sel118 - ti,j784s4-cpsw9g-phy-gmii-sel119 then:120 properties:121 ti,qsgmii-main-ports:122 minItems: 2123 maxItems: 2124 items:125 minimum: 1126 maximum: 8127 128 - if:129 not:130 properties:131 compatible:132 contains:133 enum:134 - ti,j7200-cpsw5g-phy-gmii-sel135 - ti,j721e-cpsw9g-phy-gmii-sel136 - ti,j784s4-cpsw9g-phy-gmii-sel137 then:138 properties:139 ti,qsgmii-main-ports: false140 141 - if:142 properties:143 compatible:144 contains:145 enum:146 - ti,am3352-phy-gmii-sel147 - ti,am43xx-phy-gmii-sel148 then:149 properties:150 '#phy-cells':151 const: 2152 description: |153 - CPSW port number (starting from 1)154 - RMII refclk mode155 156required:157 - compatible158 - reg159 - '#phy-cells'160 161additionalProperties: false162 163examples:164 - |165 phy_gmii_sel: phy@650 {166 compatible = "ti,am3352-phy-gmii-sel";167 reg = <0x650 0x4>;168 #phy-cells = <2>;169 };170