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1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)2# Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/3%YAML 1.24---5$id: http://devicetree.org/schemas/phy/ti,phy-j721e-wiz.yaml#6$schema: http://devicetree.org/meta-schemas/core.yaml#7 8title: TI J721E WIZ (SERDES Wrapper)9 10maintainers:11 - Kishon Vijay Abraham I <kishon@ti.com>12 13properties:14 compatible:15 enum:16 - ti,j721e-wiz-16g17 - ti,j721e-wiz-10g18 - ti,j721s2-wiz-10g19 - ti,am64-wiz-10g20 - ti,j7200-wiz-10g21 - ti,j784s4-wiz-10g22 23 power-domains:24 maxItems: 125 26 clocks:27 minItems: 328 maxItems: 429 description: clock-specifier to represent input to the WIZ30 31 clock-names:32 minItems: 333 items:34 - const: fck35 - const: core_ref_clk36 - const: ext_ref_clk37 - const: core_ref1_clk38 39 num-lanes:40 minimum: 141 maximum: 442 43 "#address-cells":44 const: 145 46 "#size-cells":47 const: 148 49 "#reset-cells":50 const: 151 52 "#clock-cells":53 const: 154 55 ranges: true56 57 typec-dir-gpios:58 maxItems: 159 description:60 GPIO to signal Type-C cable orientation for lane swap.61 If GPIO is active, lane 0 and lane 1 of SERDES will be swapped to62 achieve the functionality of an external type-C plug flip mux.63 64 typec-dir-debounce-ms:65 minimum: 10066 maximum: 100067 default: 10068 description:69 Number of milliseconds to wait before sampling typec-dir-gpio.70 If not specified, the default debounce of 100ms will be used.71 Type-C spec states minimum CC pin debounce of 100 ms and maximum72 of 200 ms. However, some solutions might need more than 200 ms.73 74 refclk-dig:75 type: object76 additionalProperties: false77 description: |78 WIZ node should have subnode for refclk_dig to select the reference79 clock source for the reference clock used in the PHY and PMA digital80 logic.81 deprecated: true82 properties:83 clocks:84 minItems: 285 maxItems: 486 description: Phandle to two (Torrent) or four (Sierra) clock nodes representing87 the inputs to refclk_dig88 89 "#clock-cells":90 const: 091 92 clock-output-names:93 maxItems: 194 95 assigned-clocks:96 maxItems: 197 98 assigned-clock-parents:99 maxItems: 1100 101 required:102 - clocks103 - "#clock-cells"104 - assigned-clocks105 - assigned-clock-parents106 107 ti,scm:108 $ref: /schemas/types.yaml#/definitions/phandle109 description: |110 phandle to System Control Module for syscon regmap access.111 112patternProperties:113 "^pll[0|1]-refclk$":114 type: object115 additionalProperties: false116 description: |117 WIZ node should have subnodes for each of the PLLs present in118 the SERDES.119 deprecated: true120 properties:121 clocks:122 maxItems: 2123 description: Phandle to clock nodes representing the two inputs to PLL.124 125 "#clock-cells":126 const: 0127 128 clock-output-names:129 maxItems: 1130 131 assigned-clocks:132 maxItems: 1133 134 assigned-clock-parents:135 maxItems: 1136 137 required:138 - clocks139 - "#clock-cells"140 - assigned-clocks141 - assigned-clock-parents142 143 "^cmn-refclk1?-dig-div$":144 type: object145 additionalProperties: false146 description:147 WIZ node should have subnodes for each of the PMA common refclock148 provided by the SERDES.149 deprecated: true150 properties:151 clocks:152 maxItems: 1153 description: Phandle to the clock node representing the input to the154 divider clock.155 156 "#clock-cells":157 const: 0158 159 clock-output-names:160 maxItems: 1161 162 required:163 - clocks164 - "#clock-cells"165 166 "^serdes@[0-9a-f]+$":167 type: object168 description: |169 WIZ node should have '1' subnode for the SERDES. It could be either170 Sierra SERDES or Torrent SERDES. Sierra SERDES should follow the171 bindings specified in172 Documentation/devicetree/bindings/phy/phy-cadence-sierra.yaml173 Torrent SERDES should follow the bindings specified in174 Documentation/devicetree/bindings/phy/phy-cadence-torrent.yaml175 176required:177 - compatible178 - power-domains179 - clocks180 - clock-names181 - num-lanes182 - "#address-cells"183 - "#size-cells"184 - "#reset-cells"185 - ranges186 187allOf:188 - if:189 properties:190 compatible:191 contains:192 const: ti,j7200-wiz-10g193 then:194 required:195 - ti,scm196 197additionalProperties: false198 199examples:200 - |201 #include <dt-bindings/soc/ti,sci_pm_domain.h>202 203 wiz@5000000 {204 compatible = "ti,j721e-wiz-16g";205 #address-cells = <1>;206 #size-cells = <1>;207 power-domains = <&k3_pds 292 TI_SCI_PD_EXCLUSIVE>;208 clocks = <&k3_clks 292 5>, <&k3_clks 292 11>, <&dummy_cmn_refclk>;209 clock-names = "fck", "core_ref_clk", "ext_ref_clk";210 assigned-clocks = <&k3_clks 292 11>, <&k3_clks 292 0>;211 assigned-clock-parents = <&k3_clks 292 15>, <&k3_clks 292 4>;212 num-lanes = <2>;213 #reset-cells = <1>;214 ranges = <0x5000000 0x5000000 0x10000>;215 216 pll0-refclk {217 clocks = <&k3_clks 293 13>, <&dummy_cmn_refclk>;218 #clock-cells = <0>;219 assigned-clocks = <&wiz1_pll0_refclk>;220 assigned-clock-parents = <&k3_clks 293 13>;221 };222 223 pll1-refclk {224 clocks = <&k3_clks 293 0>, <&dummy_cmn_refclk1>;225 #clock-cells = <0>;226 assigned-clocks = <&wiz1_pll1_refclk>;227 assigned-clock-parents = <&k3_clks 293 0>;228 };229 230 cmn-refclk-dig-div {231 clocks = <&wiz1_refclk_dig>;232 #clock-cells = <0>;233 };234 235 cmn-refclk1-dig-div {236 clocks = <&wiz1_pll1_refclk>;237 #clock-cells = <0>;238 };239 240 refclk-dig {241 clocks = <&k3_clks 292 11>, <&k3_clks 292 0>,242 <&dummy_cmn_refclk>, <&dummy_cmn_refclk1>;243 #clock-cells = <0>;244 assigned-clocks = <&wiz0_refclk_dig>;245 assigned-clock-parents = <&k3_clks 292 11>;246 };247 248 serdes@5000000 {249 compatible = "ti,sierra-phy-t0";250 reg-names = "serdes";251 reg = <0x5000000 0x10000>;252 #address-cells = <1>;253 #size-cells = <0>;254 resets = <&serdes_wiz0 0>;255 reset-names = "sierra_reset";256 clocks = <&wiz0_cmn_refclk_dig_div>, <&wiz0_cmn_refclk1_dig_div>;257 clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div";258 };259 };260