99 lines · plain
1TI PHY: DT DOCUMENTATION FOR PHYs in TI PLATFORMs2 3OMAP CONTROL PHY4 5Required properties:6 - compatible: Should be one of7 "ti,control-phy-otghs" - if it has otghs_control mailbox register as on OMAP4.8 "ti,control-phy-usb2" - if it has Power down bit in control_dev_conf register9 e.g. USB2_PHY on OMAP5.10 "ti,control-phy-pipe3" - if it has DPLL and individual Rx & Tx power control11 e.g. USB3 PHY and SATA PHY on OMAP5.12 "ti,control-phy-pcie" - for pcie to support external clock for pcie and to13 set PCS delay value.14 e.g. PCIE PHY in DRA7x15 "ti,control-phy-usb2-dra7" - if it has power down register like USB2 PHY on16 DRA7 platform.17 "ti,control-phy-usb2-am437" - if it has power down register like USB2 PHY on18 AM437 platform.19 - reg : register ranges as listed in the reg-names property20 - reg-names: "otghs_control" for control-phy-otghs21 "power", "pcie_pcs" and "control_sma" for control-phy-pcie22 "power" for all other types23 24omap_control_usb: omap-control-usb@4a002300 {25 compatible = "ti,control-phy-otghs";26 reg = <0x4a00233c 0x4>;27 reg-names = "otghs_control";28};29 30TI PIPE3 PHY31 32Required properties:33 - compatible: Should be "ti,phy-usb3", "ti,phy-pipe3-sata" or34 "ti,phy-pipe3-pcie. "ti,omap-usb3" is deprecated.35 - reg : Address and length of the register set for the device.36 - reg-names: The names of the register addresses corresponding to the registers37 filled in "reg".38 - #phy-cells: determine the number of cells that should be given in the39 phandle while referencing this phy.40 - clocks: a list of phandles and clock-specifier pairs, one for each entry in41 clock-names.42 - clock-names: should include:43 * "wkupclk" - wakeup clock.44 * "sysclk" - system clock.45 * "refclk" - reference clock.46 * "dpll_ref" - external dpll ref clk47 * "dpll_ref_m2" - external dpll ref clk48 * "phy-div" - divider for apll49 * "div-clk" - apll clock50 51Optional properties:52 - id: If there are multiple instance of the same type, in order to53 differentiate between each instance "id" can be used (e.g., multi-lane PCIe54 PHY). If "id" is not provided, it is set to default value of '1'.55 - syscon-pllreset: Handle to system control region that contains the56 CTRL_CORE_SMA_SW_0 register and register offset to the CTRL_CORE_SMA_SW_057 register that contains the SATA_PLL_SOFT_RESET bit. Only valid for sata_phy.58 - syscon-pcs : phandle/offset pair. Phandle to the system control module and the59 register offset to write the PCS delay value.60 61Deprecated properties:62 - ctrl-module : phandle of the control module used by PHY driver to power on63 the PHY.64 65Recommended properties:66 - syscon-phy-power : phandle/offset pair. Phandle to the system control67 module and the register offset to power on/off the PHY.68 69This is usually a subnode of ocp2scp to which it is connected.70 71usb3phy@4a084400 {72 compatible = "ti,phy-usb3";73 reg = <0x4a084400 0x80>,74 <0x4a084800 0x64>,75 <0x4a084c00 0x40>;76 reg-names = "phy_rx", "phy_tx", "pll_ctrl";77 ctrl-module = <&omap_control_usb>;78 #phy-cells = <0>;79 clocks = <&usb_phy_cm_clk32k>,80 <&sys_clkin>,81 <&usb_otg_ss_refclk960m>;82 clock-names = "wkupclk",83 "sysclk",84 "refclk";85};86 87sata_phy: phy@4a096000 {88 compatible = "ti,phy-pipe3-sata";89 reg = <0x4A096000 0x80>, /* phy_rx */90 <0x4A096400 0x64>, /* phy_tx */91 <0x4A096800 0x40>; /* pll_ctrl */92 reg-names = "phy_rx", "phy_tx", "pll_ctrl";93 ctrl-module = <&omap_control_sata>;94 clocks = <&sys_clkin1>, <&sata_ref_clk>;95 clock-names = "sysclk", "refclk";96 syscon-pllreset = <&scm_conf 0x3fc>;97 #phy-cells = <0>;98};99