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1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)2%YAML 1.23---4$id: http://devicetree.org/schemas/phy/xlnx,zynqmp-psgtr.yaml#5$schema: http://devicetree.org/meta-schemas/core.yaml#6 7title: Xilinx ZynqMP Gigabit Transceiver PHY8 9maintainers:10 - Laurent Pinchart <laurent.pinchart@ideasonboard.com>11 12description: |13 This binding describes the Xilinx ZynqMP Gigabit Transceiver (GTR) PHY. The14 GTR provides four lanes and is used by USB, SATA, PCIE, Display port and15 Ethernet SGMII controllers.16 17properties:18 "#phy-cells":19 const: 420 description: |21 The cells contain the following arguments.22 23 - description: The GTR lane24 minimum: 025 maximum: 326 - description: The PHY type27 enum:28 - PHY_TYPE_DP29 - PHY_TYPE_PCIE30 - PHY_TYPE_SATA31 - PHY_TYPE_SGMII32 - PHY_TYPE_USB333 - description: The PHY instance34 minimum: 035 maximum: 1 # for DP, SATA or USB36 maximum: 3 # for PCIE or SGMII37 - description: The reference clock number38 minimum: 039 maximum: 340 41 compatible:42 enum:43 - xlnx,zynqmp-psgtr-v1.144 - xlnx,zynqmp-psgtr45 46 clocks:47 minItems: 148 maxItems: 449 description: |50 Clock for each PS_MGTREFCLK[0-3] reference clock input. Unconnected51 inputs shall not have an entry.52 53 clock-names:54 minItems: 155 maxItems: 456 items:57 pattern: "^ref[0-3]$"58 59 reg:60 items:61 - description: SERDES registers block62 - description: SIOU registers block63 64 reg-names:65 items:66 - const: serdes67 - const: siou68 69 xlnx,tx-termination-fix:70 description: |71 Include this for fixing functional issue with the TX termination72 resistance in GT, which can be out of spec for the XCZU9EG silicon73 version.74 type: boolean75 76required:77 - "#phy-cells"78 - compatible79 - reg80 - reg-names81 82if:83 properties:84 compatible:85 const: xlnx,zynqmp-psgtr-v1.186 87then:88 properties:89 xlnx,tx-termination-fix: false90 91additionalProperties: false92 93examples:94 - |95 phy: phy@fd400000 {96 compatible = "xlnx,zynqmp-psgtr-v1.1";97 reg = <0xfd400000 0x40000>,98 <0xfd3d0000 0x1000>;99 reg-names = "serdes", "siou";100 clocks = <&refclks 3>, <&refclks 2>, <&refclks 0>;101 clock-names = "ref1", "ref2", "ref3";102 #phy-cells = <4>;103 };104 105...106