185 lines · yaml
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)2%YAML 1.23---4$id: http://devicetree.org/schemas/pinctrl/atmel,at91rm9200-pinctrl.yaml#5$schema: http://devicetree.org/meta-schemas/core.yaml#6 7title: Microchip PIO3 Pinmux Controller8 9maintainers:10 - Manikandan Muralidharan <manikandan.m@microchip.com>11 12description:13 The AT91 Pinmux Controller, enables the IC to share one PAD to several14 functional blocks. The sharing is done by multiplexing the PAD input/output15 signals. For each PAD there are up to 8 muxing options (called periph modes).16 Since different modules require different PAD settings (like pull up, keeper,17 etc) the controller controls also the PAD settings parameters.18 19properties:20 compatible:21 oneOf:22 - items:23 - enum:24 - atmel,at91rm9200-pinctrl25 - atmel,at91sam9x5-pinctrl26 - atmel,sama5d3-pinctrl27 - microchip,sam9x60-pinctrl28 - const: simple-mfd29 - items:30 - enum:31 - microchip,sam9x7-pinctrl32 - const: microchip,sam9x60-pinctrl33 - const: simple-mfd34 35 '#address-cells':36 const: 137 38 '#size-cells':39 const: 140 41 ranges: true42 43 atmel,mux-mask:44 $ref: /schemas/types.yaml#/definitions/uint32-matrix45 description: |46 Array of mask (periph per bank) to describe if a pin can be47 configured in this periph mode. All the periph and bank need to48 be described.49 50 #How to create such array:51 52 Each column will represent the possible peripheral of the pinctrl53 Each line will represent a pio bank54 55 #Example:56 57 In at91sam9260.dtsi,58 Peripheral: 2 ( A and B)59 Bank: 3 (A, B and C)60 61 # A B62 0xffffffff 0xffc00c3b # pioA63 0xffffffff 0x7fff3ccf # pioB64 0xffffffff 0x007fffff # pioC65 66 For each peripheral/bank we will describe in a u32 if a pin can be67 configured in it by putting 1 to the pin bit (1 << pin)68 69 Let's take the pioA on peripheral B whose value is 0xffc00c3b70 From the datasheet Table 10-2.71 Peripheral B72 PA0 MCDB073 PA1 MCCDB74 PA275 PA3 MCDB376 PA4 MCDB277 PA5 MCDB178 PA679 PA780 PA881 PA982 PA10 ETX283 PA11 ETX384 PA1285 PA1386 PA1487 PA1588 PA1689 PA1790 PA1891 PA1992 PA2093 PA2194 PA22 ETXER95 PA23 ETX296 PA24 ETX397 PA25 ERX298 PA26 ERX399 PA27 ERXCK100 PA28 ECRS101 PA29 ECOL102 PA30 RXD4103 PA31 TXD4104 105allOf:106 - $ref: pinctrl.yaml#107 108required:109 - compatible110 - ranges111 - "#address-cells"112 - "#size-cells"113 - atmel,mux-mask114 115patternProperties:116 'gpio@[0-9a-f]+$':117 $ref: /schemas/gpio/atmel,at91rm9200-gpio.yaml118 unevaluatedProperties: false119 120additionalProperties:121 type: object122 additionalProperties:123 type: object124 additionalProperties: false125 126 properties:127 atmel,pins:128 $ref: /schemas/types.yaml#/definitions/uint32-matrix129 description: |130 Each entry consists of 4 integers and represents the pins131 mux and config setting.The format is132 atmel,pins = <PIN_BANK PIN_BANK_NUM PERIPH CONFIG>.133 Supported pin number and mux varies for different SoCs, and134 are defined in <include/dt-bindings/pinctrl/at91.h>.135 items:136 items:137 - description:138 Pin bank139 - description:140 Pin bank index141 - description:142 Peripheral function143 - description:144 Pad configuration145 146examples:147 - |148 #include <dt-bindings/clock/at91.h>149 #include <dt-bindings/interrupt-controller/irq.h>150 #include <dt-bindings/pinctrl/at91.h>151 152 pinctrl@fffff400 {153 #address-cells = <1>;154 #size-cells = <1>;155 compatible = "atmel,at91rm9200-pinctrl", "simple-mfd";156 ranges = <0xfffff400 0xfffff400 0x600>;157 158 atmel,mux-mask = <159 /* A B */160 0xffffffff 0xffc00c3b /* pioA */161 0xffffffff 0x7fff3ccf /* pioB */162 0xffffffff 0x007fffff /* pioC */163 >;164 165 dbgu {166 pinctrl_dbgu: dbgu-0 {167 atmel,pins =168 <AT91_PIOB 14 AT91_PERIPH_A AT91_PINCTRL_PULL_UP169 AT91_PIOB 15 AT91_PERIPH_A AT91_PINCTRL_NONE>;170 };171 };172 173 pioA: gpio@fffff400 {174 compatible = "atmel,at91rm9200-gpio";175 reg = <0xfffff400 0x200>;176 interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>;177 #gpio-cells = <2>;178 gpio-controller;179 interrupt-controller;180 #interrupt-cells = <2>;181 clocks = <&pmc PMC_TYPE_PERIPHERAL 2>;182 };183 };184...185