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1Axis ARTPEC-6 Pin Controller2 3Required properties:4- compatible: "axis,artpec6-pinctrl".5- reg: Should contain the register physical address and length for the pin6 controller.7 8A pinctrl node should contain at least one subnode representing the pinctrl9groups available on the machine. Each subnode will list the mux function10required and what pin group it will use. Each subnode will also configure the11drive strength and bias pullup of the pin group. If either of these options is12not set, its actual value will be unspecified.13 14 15Required subnode-properties:16- function: Function to mux.17- groups: Name of the pin group to use for the function above.18 19 Available functions and groups (function: group0, group1...):20 gpio: cpuclkoutgrp0, udlclkoutgrp0, i2c1grp0, i2c2grp0,21 i2c3grp0, i2s0grp0, i2s1grp0, i2srefclkgrp0, spi0grp0,22 spi1grp0, pciedebuggrp0, uart0grp0, uart0grp1, uart0grp2,23 uart1grp0, uart1grp1, uart2grp0, uart2grp1, uart2grp2,24 uart3grp0, uart4grp0, uart4grp1, uart5grp0, uart5grp1,25 uart5nocts26 cpuclkout: cpuclkoutgrp027 udlclkout: udlclkoutgrp028 i2c1: i2c1grp029 i2c2: i2c2grp030 i2c3: i2c3grp031 i2s0: i2s0grp032 i2s1: i2s1grp033 i2srefclk: i2srefclkgrp034 spi0: spi0grp035 spi1: spi1grp036 pciedebug: pciedebuggrp037 uart0: uart0grp0, uart0grp1, uart0grp238 uart1: uart1grp0, uart1grp139 uart2: uart2grp0, uart2grp1, uart2grp240 uart3: uart3grp041 uart4: uart4grp0, uart4grp142 uart5: uart5grp0, uart5grp1, uart5nocts43 nand: nandgrp044 sdio0: sdio0grp045 sdio1: sdio1grp046 ethernet: ethernetgrp047 48 49Optional subnode-properties (see pinctrl-bindings.txt):50- drive-strength: 4, 6, 8, 9 mA. For SD and NAND pins, this is for 3.3V VCCQ3.51- bias-pull-up52- bias-disable53 54Examples:55pinctrl@f801d000 {56 compatible = "axis,artpec6-pinctrl";57 reg = <0xf801d000 0x400>;58 59 pinctrl_uart0: uart0grp {60 function = "uart0";61 groups = "uart0grp0";62 drive-strength = <4>;63 bias-pull-up;64 };65 pinctrl_uart3: uart3grp {66 function = "uart3";67 groups = "uart3grp0";68 };69};70uart0: uart@f8036000 {71 compatible = "arm,pl011", "arm,primecell";72 reg = <0xf8036000 0x1000>;73 interrupts = <0 104 IRQ_TYPE_LEVEL_HIGH>;74 clocks = <&pll2div24>, <&apb_pclk>;75 clock-names = "uart_clk", "apb_pclk";76 pinctrl-names = "default";77 pinctrl-0 = <&pinctrl_uart0>;78};79uart3: uart@f8039000 {80 compatible = "arm,pl011", "arm,primecell";81 reg = <0xf8039000 0x1000>;82 interrupts = <0 128 IRQ_TYPE_LEVEL_HIGH>;83 clocks = <&pll2div24>, <&apb_pclk>;84 clock-names = "uart_clk", "apb_pclk";85 pinctrl-names = "default";86 pinctrl-0 = <&pinctrl_uart3>;87};88