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1* Freescale IOMUX Controller (IOMUXC) for i.MX2 3The IOMUX Controller (IOMUXC), together with the IOMUX, enables the IC4to share one PAD to several functional blocks. The sharing is done by5multiplexing the PAD input/output signals. For each PAD there are up to68 muxing options (called ALT modes). Since different modules require7different PAD settings (like pull up, keeper, etc) the IOMUXC controls8also the PAD settings parameters.9 10Please refer to pinctrl-bindings.txt in this directory for details of the11common pinctrl bindings used by client devices, including the meaning of the12phrase "pin configuration node".13 14Freescale IMX pin configuration node is a node of a group of pins which can be15used for a specific device or function. This node represents both mux and config16of the pins in that group. The 'mux' selects the function mode(also named mux17mode) this pin can work on and the 'config' configures various pad settings18such as pull-up, open drain, drive strength, etc.19 20Required properties for iomux controller:21- compatible: "fsl,<soc>-iomuxc"22 Please refer to each fsl,<soc>-pinctrl.txt binding doc for supported SoCs.23 24Required properties for pin configuration node:25- fsl,pins: each entry consists of 6 integers and represents the mux and config26 setting for one pin. The first 5 integers <mux_reg conf_reg input_reg mux_val27 input_val> are specified using a PIN_FUNC_ID macro, which can be found in28 imx*-pinfunc.h under device tree source folder. The last integer CONFIG is29 the pad setting value like pull-up on this pin. And that's why fsl,pins entry30 looks like <PIN_FUNC_ID CONFIG> in the example below.31 32Bits used for CONFIG:33NO_PAD_CTL(1 << 31): indicate this pin does not need config.34 35SION(1 << 30): Software Input On Field.36Force the selected mux mode input path no matter of MUX_MODE functionality.37By default the input path is determined by functionality of the selected38mux mode (regular).39 40Other bits are used for PAD setting.41Please refer to each fsl,<soc>-pinctrl,txt binding doc for SoC specific part42of bits definitions.43 44NOTE:45Some requirements for using fsl,imx-pinctrl binding:461. We have pin function node defined under iomux controller node to represent47 what pinmux functions this SoC supports.482. The pin configuration node intends to work on a specific function should49 to be defined under that specific function node.50 The function node's name should represent well about what function51 this group of pins in this pin configuration node are working on.523. The driver can use the function node's name and pin configuration node's53 name describe the pin function and group hierarchy.54 For example, Linux IMX pinctrl driver takes the function node's name55 as the function name and pin configuration node's name as group name to56 create the map table.574. Each pin configuration node should have a phandle, devices can set pins58 configurations by referring to the phandle of that pin configuration node.59 60Examples:61usdhc@219c000 { /* uSDHC4 */62 non-removable;63 vmmc-supply = <®_3p3v>;64 pinctrl-names = "default";65 pinctrl-0 = <&pinctrl_usdhc4_1>;66};67 68iomuxc@20e0000 {69 compatible = "fsl,imx6q-iomuxc";70 reg = <0x020e0000 0x4000>;71 72 /* shared pinctrl settings */73 usdhc4 {74 pinctrl_usdhc4_1: usdhc4grp-1 {75 fsl,pins = <76 MX6QDL_PAD_SD4_CMD__SD4_CMD 0x1705977 MX6QDL_PAD_SD4_CLK__SD4_CLK 0x1005978 MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x1705979 MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x1705980 MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x1705981 MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x1705982 MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x1705983 MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x1705984 MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x1705985 MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x1705986 >;87 };88 ....89};90Refer to the IOMUXC controller chapter in imx6q datasheet,910x17059 means enable hysteresis, 47KOhm Pull Up, 50Mhz speed,9280Ohm driver strength and Fast Slew Rate.93User should refer to each SoC spec to set the correct value.94