80 lines · yaml
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)2%YAML 1.23---4$id: http://devicetree.org/schemas/pinctrl/fsl,imxrt1050.yaml#5$schema: http://devicetree.org/meta-schemas/core.yaml#6 7title: Freescale IMXRT1050 IOMUX Controller8 9maintainers:10 - Giulio Benetti <giulio.benetti@benettiengineering.com>11 - Jesse Taube <Mr.Bossman075@gmail.com>12 13description:14 Please refer to fsl,imx-pinctrl.txt and pinctrl-bindings.txt in this directory15 for common binding part and usage.16 17properties:18 compatible:19 const: fsl,imxrt1050-iomuxc20 21 reg:22 maxItems: 123 24# Client device subnode's properties25patternProperties:26 'grp$':27 type: object28 description:29 Pinctrl node's client devices use subnodes for desired pin configuration.30 Client device subnodes use below standard properties.31 32 properties:33 fsl,pins:34 description:35 each entry consists of 6 integers and represents the mux and config36 setting for one pin. The first 5 integers <mux_reg conf_reg input_reg37 mux_val input_val> are specified using a PIN_FUNC_ID macro, which can38 be found in <arch/arm/boot/dts/imxrt1050-pinfunc.h>. The last39 integer CONFIG is the pad setting value like pull-up on this pin. Please40 refer to i.MXRT1050 Reference Manual for detailed CONFIG settings.41 $ref: /schemas/types.yaml#/definitions/uint32-matrix42 items:43 items:44 - description: |45 "mux_reg" indicates the offset of mux register.46 - description: |47 "conf_reg" indicates the offset of pad configuration register.48 - description: |49 "input_reg" indicates the offset of select input register.50 - description: |51 "mux_val" indicates the mux value to be applied.52 - description: |53 "input_val" indicates the select input value to be applied.54 - description: |55 "pad_setting" indicates the pad configuration value to be applied.56 57 required:58 - fsl,pins59 60 additionalProperties: false61 62required:63 - compatible64 - reg65 66additionalProperties: false67 68examples:69 - |70 iomuxc: iomuxc@401f8000 {71 compatible = "fsl,imxrt1050-iomuxc";72 reg = <0x401f8000 0x4000>;73 74 pinctrl_lpuart1: lpuart1grp {75 fsl,pins =76 <0x0EC 0x2DC 0x000 0x2 0x0 0xf1>,77 <0x0F0 0x2E0 0x000 0x2 0x0 0xf1>;78 };79 };80