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1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)2%YAML 1.23---4$id: http://devicetree.org/schemas/pinctrl/fsl,imxrt1170.yaml#5$schema: http://devicetree.org/meta-schemas/core.yaml#6 7title: Freescale i.MXRT1170 IOMUX Controller8 9maintainers:10 - Giulio Benetti <giulio.benetti@benettiengineering.com>11 - Jesse Taube <Mr.Bossman075@gmail.com>12 13description:14 Please refer to fsl,imx-pinctrl.txt and pinctrl-bindings.txt in this directory15 for common binding part and usage.16 17properties:18 compatible:19 const: fsl,imxrt1170-iomuxc20 21 reg:22 maxItems: 123 24# Client device subnode's properties25patternProperties:26 'grp$':27 type: object28 description:29 Pinctrl node's client devices use subnodes for desired pin configuration.30 Client device subnodes use below standard properties.31 32 properties:33 fsl,pins:34 description:35 each entry consists of 6 integers and represents the mux and config36 setting for one pin. The first 5 integers <mux_reg conf_reg input_reg37 mux_val input_val> are specified using a PIN_FUNC_ID macro, which can38 be found in <arch/arm/boot/dts/imxrt1170-pinfunc.h>. The last39 integer CONFIG is the pad setting value like pull-up on this pin. Please40 refer to i.MXRT1170 Reference Manual for detailed CONFIG settings.41 $ref: /schemas/types.yaml#/definitions/uint32-matrix42 items:43 items:44 - description: |45 "mux_reg" indicates the offset of mux register.46 - description: |47 "conf_reg" indicates the offset of pad configuration register.48 - description: |49 "input_reg" indicates the offset of select input register.50 - description: |51 "mux_val" indicates the mux value to be applied.52 - description: |53 "input_val" indicates the select input value to be applied.54 - description: |55 "pad_setting" indicates the pad configuration value to be applied.56 required:57 - fsl,pins58 59 additionalProperties: false60 61required:62 - compatible63 - reg64 65additionalProperties: false66 67examples:68 - |69 iomuxc: iomuxc@400e8000 {70 compatible = "fsl,imxrt1170-iomuxc";71 reg = <0x400e8000 0x4000>;72 pinctrl_lpuart1: lpuart1grp {73 fsl,pins =74 <0x16C 0x3B0 0x620 0x0 0x0 0xf1>,75 <0x170 0x3B4 0x61C 0x0 0x0 0xf1>;76 };77 };78