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1Imagination Technologies Pistachio SoC pin controllers2======================================================3 4The pin controllers on Pistachio are a combined GPIO controller, (GPIO)5interrupt controller, and pinmux + pinconf device. The system ("east") pin6controller on Pistachio has 99 pins, 90 of which are MFIOs which can be7configured as GPIOs. The 90 GPIOs are divided into 6 banks of up to 16 GPIOs8each. The GPIO banks are represented as sub-nodes of the pad controller node.9 10Please refer to pinctrl-bindings.txt, ../gpio/gpio.txt, and11../interrupt-controller/interrupts.txt for generic information regarding12pin controller, GPIO, and interrupt bindings.13 14Required properties for pin controller node:15--------------------------------------------16 - compatible: "img,pistachio-system-pinctrl".17 - reg: Address range of the pinctrl registers.18 19Required properties for GPIO bank sub-nodes:20--------------------------------------------21 - interrupts: Interrupt line for the GPIO bank.22 - gpio-controller: Indicates the device is a GPIO controller.23 - #gpio-cells: Must be two. The first cell is the GPIO pin number and the24 second cell indicates the polarity. See <dt-bindings/gpio/gpio.h> for25 a list of possible values.26 - interrupt-controller: Indicates the device is an interrupt controller.27 - #interrupt-cells: Must be two. The first cell is the GPIO pin number and28 the second cell encodes the interrupt flags. See29 <dt-bindings/interrupt-controller/irq.h> for a list of valid flags.30 31Note that the N GPIO bank sub-nodes *must* be named gpio0, gpio1, ... gpioN-1.32 33Required properties for pin configuration sub-nodes:34----------------------------------------------------35 - pins: List of pins to which the configuration applies. See below for a36 list of possible pins.37 38Optional properties for pin configuration sub-nodes:39----------------------------------------------------40 - function: Mux function for the specified pins. This is not applicable for41 non-MFIO pins. See below for a list of valid functions for each pin.42 - bias-high-impedance: Enable high-impedance mode.43 - bias-pull-up: Enable weak pull-up.44 - bias-pull-down: Enable weak pull-down.45 - bias-bus-hold: Enable bus-keeper mode.46 - drive-strength: Drive strength in mA. Supported values: 2, 4, 8, 12.47 - input-schmitt-enable: Enable Schmitt trigger.48 - input-schmitt-disable: Disable Schmitt trigger.49 - slew-rate: Slew rate control. 0 for slow, 1 for fast.50 51Pin Functions52--- ---------53mfio0 spim154mfio1 spim1, spim0, uart155mfio2 spim1, spim0, uart156mfio3 spim157mfio4 spim158mfio5 spim159mfio6 spim160mfio7 spim161mfio8 spim062mfio9 spim063mfio10 spim064mfio11 spis65mfio12 spis66mfio13 spis67mfio14 spis68mfio15 sdhost, mips_trace_clk, mips_trace_data69mfio16 sdhost, mips_trace_dint, mips_trace_data70mfio17 sdhost, mips_trace_trigout, mips_trace_data71mfio18 sdhost, mips_trace_trigin, mips_trace_data72mfio19 sdhost, mips_trace_dm, mips_trace_data73mfio20 sdhost, mips_trace_probe_n, mips_trace_data74mfio21 sdhost, mips_trace_data75mfio22 sdhost, mips_trace_data76mfio23 sdhost77mfio24 sdhost78mfio25 sdhost79mfio26 sdhost80mfio27 sdhost81mfio28 i2c0, spim082mfio29 i2c0, spim083mfio30 i2c1, spim084mfio31 i2c1, spim185mfio32 i2c286mfio33 i2c287mfio34 i2c388mfio35 i2c389mfio36 i2s_out, audio_clk_in90mfio37 i2s_out, debug_raw_cca_ind91mfio38 i2s_out, debug_ed_sec20_cca_ind92mfio39 i2s_out, debug_ed_sec40_cca_ind93mfio40 i2s_out, debug_agc_done_094mfio41 i2s_out, debug_agc_done_195mfio42 i2s_out, debug_ed_cca_ind96mfio43 i2s_out, debug_s2l_done97mfio44 i2s_out98mfio45 i2s_dac_clk, audio_sync99mfio46 audio_trigger100mfio47 i2s_in101mfio48 i2s_in102mfio49 i2s_in103mfio50 i2s_in104mfio51 i2s_in105mfio52 i2s_in106mfio53 i2s_in107mfio54 i2s_in, spdif_in108mfio55 uart0, spim0, spim1109mfio56 uart0, spim0, spim1110mfio57 uart0, spim0, spim1111mfio58 uart0, spim1112mfio59 uart1113mfio60 uart1114mfio61 spdif_out115mfio62 spdif_in116mfio63 eth, mips_trace_clk, mips_trace_data117mfio64 eth, mips_trace_dint, mips_trace_data118mfio65 eth, mips_trace_trigout, mips_trace_data119mfio66 eth, mips_trace_trigin, mips_trace_data120mfio67 eth, mips_trace_dm, mips_trace_data121mfio68 eth, mips_trace_probe_n, mips_trace_data122mfio69 eth, mips_trace_data123mfio70 eth, mips_trace_data124mfio71 eth125mfio72 ir126mfio73 pwmpdm, mips_trace_clk, sram_debug127mfio74 pwmpdm, mips_trace_dint, sram_debug128mfio75 pwmpdm, mips_trace_trigout, rom_debug129mfio76 pwmpdm, mips_trace_trigin, rom_debug130mfio77 mdc_debug, mips_trace_dm, rpu_debug131mfio78 mdc_debug, mips_trace_probe_n, rpu_debug132mfio79 ddr_debug, mips_trace_data, mips_debug133mfio80 ddr_debug, mips_trace_data, mips_debug134mfio81 dreq0, mips_trace_data, eth_debug135mfio82 dreq1, mips_trace_data, eth_debug136mfio83 mips_pll_lock, mips_trace_data, usb_debug137mfio84 audio_pll_lock, mips_trace_data, usb_debug138mfio85 rpu_v_pll_lock, mips_trace_data, sdhost_debug139mfio86 rpu_l_pll_lock, mips_trace_data, sdhost_debug140mfio87 sys_pll_lock, dreq2, socif_debug141mfio88 wifi_pll_lock, dreq3, socif_debug142mfio89 bt_pll_lock, dreq4, dreq5143tck144trstn145tdi146tms147tdo148jtag_comply149safe_mode150por_disable151resetn152 153Example:154--------155pinctrl@18101c00 {156 compatible = "img,pistachio-system-pinctrl";157 reg = <0x18101C00 0x400>;158 159 gpio0: gpio0 {160 interrupts = <GIC_SHARED 71 IRQ_TYPE_LEVEL_HIGH>;161 162 gpio-controller;163 #gpio-cells = <2>;164 165 interrupt-controller;166 #interrupt-cells = <2>;167 };168 169 ...170 171 gpio5: gpio5 {172 interrupts = <GIC_SHARED 76 IRQ_TYPE_LEVEL_HIGH>;173 174 gpio-controller;175 #gpio-cells = <2>;176 177 interrupt-controller;178 #interrupt-cells = <2>;179 };180 181 ...182 183 uart0_xfer: uart0-xfer {184 uart0-rxd {185 pins = "mfio55";186 function = "uart0";187 };188 uart0-txd {189 pins = "mfio56";190 function = "uart0";191 };192 };193 194 uart0_rts_cts: uart0-rts-cts {195 uart0-rts {196 pins = "mfio57";197 function = "uart0";198 };199 uart0-cts {200 pins = "mfio58";201 function = "uart0";202 };203 };204};205 206uart@... {207 ...208 pinctrl-names = "default";209 pinctrl-0 = <&uart0_xfer>, <&uart0_rts_cts>;210 ...211};212 213usb_vbus: fixed-regulator {214 ...215 gpio = <&gpio5 6 GPIO_ACTIVE_HIGH>;216 ...217};218