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1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)2%YAML 1.23---4$id: http://devicetree.org/schemas/pinctrl/intel,pinctrl-keembay.yaml#5$schema: http://devicetree.org/meta-schemas/core.yaml#6 7title: Intel Keem Bay pin controller8 9maintainers:10 - Lakshmi Sowjanya D <lakshmi.sowjanya.d@intel.com>11 12description: |13 Intel Keem Bay SoC integrates a pin controller which enables control14 of pin directions, input/output values and configuration15 for a total of 80 pins.16 17properties:18 compatible:19 const: intel,keembay-pinctrl20 21 reg:22 maxItems: 223 24 gpio-controller: true25 26 '#gpio-cells':27 const: 228 29 ngpios:30 description: The number of GPIOs exposed.31 const: 8032 33 interrupts:34 description:35 Specifies the interrupt lines to be used by the controller.36 Each interrupt line is shared by upto 4 GPIO lines.37 maxItems: 838 39 interrupt-controller: true40 41 '#interrupt-cells':42 const: 243 44patternProperties:45 '^gpio@[0-9a-f]*$':46 type: object47 additionalProperties: false48 49 description:50 Child nodes can be specified to contain pin configuration information,51 which can then be utilized by pinctrl client devices.52 The following properties are supported.53 54 properties:55 pins:56 description: |57 The name(s) of the pins to be configured in the child node.58 Supported pin names are "GPIO0" up to "GPIO79".59 60 bias-disable: true61 62 bias-pull-down: true63 64 bias-pull-up: true65 66 drive-strength:67 description: IO pads drive strength in milli Ampere.68 enum: [2, 4, 8, 12]69 70 bias-bus-hold:71 type: boolean72 73 input-schmitt-enable:74 type: boolean75 76 slew-rate:77 description: GPIO slew rate control.78 0 - Fast(~100MHz)79 1 - Slow(~50MHz)80 enum: [0, 1]81 82additionalProperties: false83 84required:85 - compatible86 - reg87 - gpio-controller88 - ngpios89 - '#gpio-cells'90 - interrupts91 - interrupt-controller92 - '#interrupt-cells'93 94examples:95 - |96 #include <dt-bindings/interrupt-controller/arm-gic.h>97 #include <dt-bindings/interrupt-controller/irq.h>98 // Example 199 gpio@0 {100 compatible = "intel,keembay-pinctrl";101 reg = <0x600b0000 0x88>,102 <0x600b0190 0x1ac>;103 gpio-controller;104 ngpios = <0x50>;105 #gpio-cells = <0x2>;106 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>,107 <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,108 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,109 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,110 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,111 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,112 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,113 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;114 interrupt-controller;115 #interrupt-cells = <2>;116 };117 118 // Example 2119 gpio@1 {120 compatible = "intel,keembay-pinctrl";121 reg = <0x600c0000 0x88>,122 <0x600c0190 0x1ac>;123 gpio-controller;124 ngpios = <0x50>;125 #gpio-cells = <0x2>;126 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>,127 <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,128 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,129 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,130 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,131 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,132 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,133 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;134 interrupt-controller;135 #interrupt-cells = <2>;136 };137