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1* Marvell Armada 37xx SoC pin and gpio controller2 3Each Armada 37xx SoC come with two pin and gpio controller one for the4south bridge and the other for the north bridge.5 6Inside this set of register the gpio latch allows exposing some7configuration of the SoC and especially the clock frequency of the8xtal. Hence, this node is a represent as syscon allowing sharing the9register between multiple hardware block.10 11GPIO and pin controller:12------------------------13 14Main node:15 16Refer to pinctrl-bindings.txt in this directory for details of the17common pinctrl bindings used by client devices, including the meaning18of the phrase "pin configuration node".19 20Required properties for pinctrl driver:21 22- compatible: "marvell,armada3710-sb-pinctrl", "syscon, "simple-mfd"23 for the south bridge24 "marvell,armada3710-nb-pinctrl", "syscon, "simple-mfd"25 for the north bridge26- reg: The first set of register are for pinctrl/gpio and the second27 set for the interrupt controller28- interrupts: list of the interrupt use by the gpio29 30Available groups and functions for the North bridge:31 32group: jtag33 - pins 20-2434 - functions jtag, gpio35 36group sdio037 - pins 8-1038 - functions sdio, gpio39 40group emmc_nb41 - pins 27-3542 - functions emmc, gpio43 44group pwm045 - pin 11 (GPIO1-11)46 - functions pwm, led, gpio47 48group pwm149 - pin 1250 - functions pwm, led, gpio51 52group pwm253 - pin 1354 - functions pwm, led, gpio55 56group pwm357 - pin 1458 - functions pwm, led, gpio59 60group pmic161 - pin 762 - functions pmic, gpio63 64group pmic065 - pin 666 - functions pmic, gpio67 68group i2c269 - pins 2-370 - functions i2c, gpio71 72group i2c173 - pins 0-174 - functions i2c, gpio75 76group spi_cs177 - pin 1778 - functions spi, gpio79 80group spi_cs281 - pin 1882 - functions spi, gpio83 84group spi_cs385 - pin 1986 - functions spi, gpio87 88group onewire89 - pin 490 - functions onewire, gpio91 92group uart193 - pins 25-2694 - functions uart, gpio95 96group spi_quad97 - pins 15-1698 - functions spi, gpio99 100group uart2101 - pins 9-10 and 18-19102 - functions uart, gpio103 104Available groups and functions for the South bridge:105 106group usb32_drvvbus0107 - pin 36108 - functions drvbus, gpio109 110group usb2_drvvbus1111 - pin 37112 - functions drvbus, gpio113 114group sdio_sb115 - pins 60-65116 - functions sdio, gpio117 118group rgmii119 - pins 42-53120 - functions mii, gpio121 122group pcie1123 - pins 39124 - functions pcie, gpio125 126group pcie1_clkreq127 - pins 40128 - functions pcie, gpio129 130group pcie1_wakeup131 - pins 41132 - functions pcie, gpio133 134group smi135 - pins 54-55136 - functions smi, gpio137 138group ptp139 - pins 56140 - functions ptp, gpio141 142group ptp_clk143 - pin 57144 - functions ptp, mii145 146group ptp_trig147 - pin 58148 - functions ptp, mii149 150group mii_col151 - pin 59152 - functions mii, mii_err153 154GPIO subnode:155 156Please refer to gpio.txt in this directory for details of gpio-ranges property157and the common GPIO bindings used by client devices.158 159Required properties for gpio driver under the gpio subnode:160- interrupts: List of interrupt specifier for the controllers interrupt.161- gpio-controller: Marks the device node as a gpio controller.162- #gpio-cells: Should be 2. The first cell is the GPIO number and the163 second cell specifies GPIO flags, as defined in164 <dt-bindings/gpio/gpio.h>. Only the GPIO_ACTIVE_HIGH and165 GPIO_ACTIVE_LOW flags are supported.166- gpio-ranges: Range of pins managed by the GPIO controller.167 168Xtal Clock bindings for Marvell Armada 37xx SoCs169------------------------------------------------170 171see Documentation/devicetree/bindings/clock/armada3700-xtal-clock.txt172 173 174Example:175pinctrl_sb: pinctrl-sb@18800 {176 compatible = "marvell,armada3710-sb-pinctrl", "syscon", "simple-mfd";177 reg = <0x18800 0x100>, <0x18C00 0x20>;178 gpio {179 #gpio-cells = <2>;180 gpio-ranges = <&pinctrl_sb 0 0 29>;181 gpio-controller;182 interrupts =183 <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,184 <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>,185 <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>,186 <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,187 <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;188 };189 190 rgmii_pins: mii-pins {191 groups = "rgmii";192 function = "mii";193 };194 195};196