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1* Marvell Dove SoC pinctrl driver for mpp2 3Please refer to marvell,mvebu-pinctrl.txt in this directory for common binding4part and usage.5 6Required properties:7- compatible: "marvell,dove-pinctrl"8- clocks: (optional) phandle of pdma clock9- reg: register specifiers of MPP, MPP4, and PMU MPP registers10 11Available mpp pins/groups and functions:12Note: brackets (x) are not part of the mpp name for marvell,function and given13only for more detailed description in this document.14Note: pmu* also allows for Power Management functions listed below15 16name pins functions17================================================================================18mpp0 0 gpio, pmu, uart2(rts), sdio0(cd), lcd0(pwm), pmu*19mpp1 1 gpio, pmu, uart2(cts), sdio0(wp), lcd1(pwm), pmu*20mpp2 2 gpio, pmu, uart2(txd), sdio0(buspwr), sata(prsnt),21 uart1(rts), pmu*22mpp3 3 gpio, pmu, uart2(rxd), sdio0(ledctrl), sata(act),23 uart1(cts), lcd-spi(cs1), pmu*24mpp4 4 gpio, pmu, uart3(rts), sdio1(cd), spi1(miso), pmu*25mpp5 5 gpio, pmu, uart3(cts), sdio1(wp), spi1(cs), pmu*26mpp6 6 gpio, pmu, uart3(txd), sdio1(buspwr), spi1(mosi), pmu*27mpp7 7 gpio, pmu, uart3(rxd), sdio1(ledctrl), spi1(sck), pmu*28mpp8 8 gpio, pmu, watchdog(rstout), pmu*29mpp9 9 gpio, pmu, pex1(clkreq), pmu*30mpp10 10 gpio, pmu, ssp(sclk), pmu*31mpp11 11 gpio, pmu, sata(prsnt), sata-1(act), sdio0(ledctrl),32 sdio1(ledctrl), pex0(clkreq), pmu*33mpp12 12 gpio, pmu, uart2(rts), audio0(extclk), sdio1(cd),34 sata(act), pmu*35mpp13 13 gpio, pmu, uart2(cts), audio1(extclk), sdio1(wp),36 ssp(extclk), pmu*37mpp14 14 gpio, pmu, uart2(txd), sdio1(buspwr), ssp(rxd), pmu*38mpp15 15 gpio, pmu, uart2(rxd), sdio1(ledctrl), ssp(sfrm), pmu*39mpp16 16 gpio, uart3(rts), sdio0(cd), ac97(sdi1), lcd-spi(cs1)40mpp17 17 gpio, uart3(cts), sdio0(wp), ac97(sdi2), twsi(sda),41 ac97-1(sysclko)42mpp18 18 gpio, uart3(txd), sdio0(buspwr), ac97(sdi3), lcd0(pwm)43mpp19 19 gpio, uart3(rxd), sdio0(ledctrl), twsi(sck)44mpp20 20 gpio, sdio0(cd), sdio1(cd), spi1(miso), lcd-spi(miso),45 ac97(sysclko)46mpp21 21 gpio, sdio0(wp), sdio1(wp), spi1(cs), lcd-spi(cs0),47 uart1(cts), ssp(sfrm)48mpp22 22 gpio, sdio0(buspwr), sdio1(buspwr), spi1(mosi),49 lcd-spi(mosi), uart1(cts), ssp(txd)50mpp23 23 gpio, sdio0(ledctrl), sdio1(ledctrl), spi1(sck),51 lcd-spi(sck), ssp(sclk)52mpp_camera 24-39 gpio, camera53mpp_sdio0 40-45 gpio, sdio054mpp_sdio1 46-51 gpio, sdio155mpp_audio1 52-57 gpio, i2s1/spdifo, i2s1, spdifo, twsi, ssp/spdifo, ssp,56 ssp/twsi57mpp_spi0 58-61 gpio, spi058mpp_uart1 62-63 gpio, uart159mpp_nand 64-71 gpo, nand60audio0 - i2s, ac9761twsi - none, opt1, opt2, opt362 63Power Management functions (pmu*):64pmu-nc Pin not driven by any PM function65pmu-low Pin driven low (0)66pmu-high Pin driven high (1)67pmic(sdi) Pin is used for PMIC SDI68cpu-pwr-down Pin is used for CPU_PWRDWN69standby-pwr-down Pin is used for STBY_PWRDWN70core-pwr-good Pin is used for CORE_PWR_GOOD (Pins 0-7 only)71cpu-pwr-good Pin is used for CPU_PWR_GOOD (Pins 8-15 only)72bat-fault Pin is used for BATTERY_FAULT73ext0-wakeup Pin is used for EXT0_WU74ext1-wakeup Pin is used for EXT0_WU75ext2-wakeup Pin is used for EXT0_WU76pmu-blink Pin is used for blink function77 78Notes:79* group "mpp_audio1" allows the following functions and gpio pins:80 - gpio : gpio on pins 52-5781 - i2s1/spdifo : audio1 i2s on pins 52-55 and spdifo on 57, no gpios82 - i2s1 : audio1 i2s on pins 52-55, gpio on pins 56,5783 - spdifo : spdifo on pin 57, gpio on pins 52-5584 - twsi : twsi on pins 56,57, gpio on pins 52-5585 - ssp/spdifo : ssp on pins 52-55, spdifo on pin 57, no gpios86 - ssp : ssp on pins 52-55, gpio on pins 56,5787 - ssp/twsi : ssp on pins 52-55, twsi on pins 56,57, no gpios88* group "audio0" internally muxes i2s0 or ac97 controller to the dedicated89 audio0 pins.90* group "twsi" internally muxes twsi controller to the dedicated or option pins.91