400 lines · yaml
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)2%YAML 1.23---4$id: http://devicetree.org/schemas/pinctrl/mediatek,mt7622-pinctrl.yaml#5$schema: http://devicetree.org/meta-schemas/core.yaml#6 7title: MediaTek MT7622 Pin Controller8 9maintainers:10 - Sean Wang <sean.wang@kernel.org>11 12description:13 The MediaTek's MT7622 Pin controller is used to control SoC pins.14 15properties:16 compatible:17 enum:18 - mediatek,mt7622-pinctrl19 - mediatek,mt7629-pinctrl20 21 reg:22 maxItems: 123 24 reg-names:25 items:26 - const: eint27 28 gpio-controller: true29 30 "#gpio-cells":31 const: 232 description:33 Number of cells in GPIO specifier. Since the generic GPIO binding is used,34 the amount of cells must be specified as 2. See the below mentioned gpio35 binding representation for description of particular cells.36 37 gpio-ranges:38 maxItems: 139 40 interrupt-controller: true41 42 interrupts:43 maxItems: 144 45 "#interrupt-cells":46 const: 247 48allOf:49 - $ref: pinctrl.yaml#50 51required:52 - compatible53 - reg54 - gpio-controller55 - "#gpio-cells"56 57if:58 required:59 - interrupt-controller60then:61 required:62 - reg-names63 - interrupts64 - "#interrupt-cells"65 66patternProperties:67 '-pins(-[a-z]+)?$':68 type: object69 additionalProperties: false70 patternProperties:71 '^mux(-|$)':72 type: object73 additionalProperties: false74 description:75 pinmux configuration nodes.76 $ref: /schemas/pinctrl/pinmux-node.yaml77 properties:78 function:79 description:80 A string containing the name of the function to mux to the group.81 enum: [antsel, emmc, eth, i2c, i2s, ir, led, flash, pcie, pmic, pwm,82 sd, spi, tdm, uart, watchdog, wifi]83 84 groups:85 description:86 An array of strings. Each string contains the name of a group.87 88 drive-strength:89 enum: [4, 8, 12, 16]90 91 required:92 - groups93 - function94 95 allOf:96 - if:97 properties:98 function:99 const: antsel100 then:101 properties:102 groups:103 items:104 enum: [antsel0, antsel1, antsel2, antsel3, antsel4, antsel5,105 antsel6, antsel7, antsel8, antsel9, antsel10,106 antsel11, antsel12, antsel13, antsel14, antsel15,107 antsel16, antsel17, antsel18, antsel19, antsel20,108 antsel21, antsel22, antsel23, antsel24, antsel25,109 antsel26, antsel27, antsel28, antsel29]110 - if:111 properties:112 function:113 const: emmc114 then:115 properties:116 groups:117 items:118 enum: [emmc, emmc_rst]119 - if:120 properties:121 function:122 const: eth123 then:124 properties:125 groups:126 items:127 enum: [esw, esw_p0_p1, esw_p2_p3_p4, rgmii_via_esw,128 rgmii_via_gmac1, rgmii_via_gmac2, mdc_mdio]129 - if:130 properties:131 function:132 const: i2c133 then:134 properties:135 groups:136 enum: [i2c0, i2c_0, i2c_1, i2c1_0, i2c1_1, i2c1_2, i2c2_0,137 i2c2_1, i2c2_2]138 - if:139 properties:140 function:141 const: i2s142 then:143 properties:144 groups:145 items:146 enum: [i2s_in_mclk_bclk_ws, i2s1_in_data, i2s2_in_data,147 i2s3_in_data, i2s4_in_data, i2s_out_mclk_bclk_ws,148 i2s1_out_data, i2s2_out_data, i2s3_out_data,149 i2s4_out_data]150 - if:151 properties:152 function:153 const: ir154 then:155 properties:156 groups:157 enum: [ir_0_tx, ir_1_tx, ir_2_tx, ir_0_rx, ir_1_rx, ir_2_rx]158 - if:159 properties:160 function:161 const: led162 then:163 properties:164 groups:165 enum: [ephy_leds, ephy0_led, ephy1_led, ephy2_led, ephy3_led,166 ephy4_led, wled, wf2g_led, wf5g_led]167 - if:168 properties:169 function:170 const: flash171 then:172 properties:173 groups:174 enum: [par_nand, snfi, spi_nor]175 - if:176 properties:177 function:178 const: pcie179 then:180 properties:181 groups:182 items:183 enum: [pcie0_0_waken, pcie0_1_waken, pcie1_0_waken,184 pcie0_0_clkreq, pcie0_1_clkreq, pcie1_0_clkreq,185 pcie0_pad_perst, pcie1_pad_perst, pcie_pereset,186 pcie_wake, pcie_clkreq]187 - if:188 properties:189 function:190 const: pmic191 then:192 properties:193 groups:194 enum: [pmic_bus]195 - if:196 properties:197 function:198 const: pwm199 then:200 properties:201 groups:202 items:203 enum: [pwm_ch1_0, pwm_ch1_1, pwm_ch1_2, pwm_ch2_0, pwm_ch2_1,204 pwm_ch2_2, pwm_ch3_0, pwm_ch3_1, pwm_ch3_2, pwm_ch4_0,205 pwm_ch4_1, pwm_ch4_2, pwm_ch4_3, pwm_ch5_0, pwm_ch5_1,206 pwm_ch5_2, pwm_ch6_0, pwm_ch6_1, pwm_ch6_2, pwm_ch6_3,207 pwm_ch7_0, pwm_0, pwm_1]208 - if:209 properties:210 function:211 const: sd212 then:213 properties:214 groups:215 enum: [sd_0, sd_1]216 - if:217 properties:218 function:219 const: spi220 then:221 properties:222 groups:223 enum: [spic0_0, spic0_1, spic1_0, spic1_1, spic2_0_wp_hold,224 spic2_0, spi_0, spi_1, spi_wp, spi_hold]225 - if:226 properties:227 function:228 const: tdm229 then:230 properties:231 groups:232 enum: [tdm_0_out_mclk_bclk_ws, tdm_0_in_mclk_bclk_ws,233 tdm_0_out_data, tdm_0_in_data, tdm_1_out_mclk_bclk_ws,234 tdm_1_in_mclk_bclk_ws, tdm_1_out_data, tdm_1_in_data]235 - if:236 properties:237 function:238 const: uart239 then:240 properties:241 groups:242 enum: [uart0_0_tx_rx, uart1_0_tx_rx, uart1_0_rts_cts,243 uart1_1_tx_rx, uart1_1_rts_cts, uart2_0_tx_rx,244 uart2_0_rts_cts, uart2_1_tx_rx, uart2_1_rts_cts,245 uart2_2_tx_rx, uart2_2_rts_cts, uart2_3_tx_rx,246 uart3_0_tx_rx, uart3_1_tx_rx, uart3_1_rts_cts,247 uart4_0_tx_rx, uart4_1_tx_rx, uart4_1_rts_cts,248 uart4_2_tx_rx, uart4_2_rts_cts, uart0_txd_rxd,249 uart1_0_txd_rxd, uart1_0_cts_rts, uart1_1_txd_rxd,250 uart1_1_cts_rts, uart2_0_txd_rxd, uart2_0_cts_rts,251 uart2_1_txd_rxd, uart2_1_cts_rts]252 - if:253 properties:254 function:255 const: watchdog256 then:257 properties:258 groups:259 enum: [watchdog]260 - if:261 properties:262 function:263 const: wifi264 then:265 properties:266 groups:267 enum: [wf0_2g, wf0_5g]268 269 '^conf(-|$)':270 type: object271 additionalProperties: false272 description:273 pinconf configuration nodes.274 $ref: /schemas/pinctrl/pincfg-node.yaml275 276 properties:277 groups:278 description:279 An array of strings. Each string contains the name of a group.280 Valid values are the same as the pinmux node.281 282 pins:283 description:284 An array of strings. Each string contains the name of a pin.285 items:286 enum: [GPIO_A, I2S1_IN, I2S1_OUT, I2S_BCLK, I2S_WS, I2S_MCLK, TXD0,287 RXD0, SPI_WP, SPI_HOLD, SPI_CLK, SPI_MOSI, SPI_MISO, SPI_CS,288 I2C_SDA, I2C_SCL, I2S2_IN, I2S3_IN, I2S4_IN, I2S2_OUT,289 I2S3_OUT, I2S4_OUT, GPIO_B, MDC, MDIO, G2_TXD0, G2_TXD1,290 G2_TXD2, G2_TXD3, G2_TXEN, G2_TXC, G2_RXD0, G2_RXD1, G2_RXD2,291 G2_RXD3, G2_RXDV, G2_RXC, NCEB, NWEB, NREB, NDL4, NDL5, NDL6,292 NDL7, NRB, NCLE, NALE, NDL0, NDL1, NDL2, NDL3, MDI_TP_P0,293 MDI_TN_P0, MDI_RP_P0, MDI_RN_P0, MDI_TP_P1, MDI_TN_P1,294 MDI_RP_P1, MDI_RN_P1, MDI_RP_P2, MDI_RN_P2, MDI_TP_P2,295 MDI_TN_P2, MDI_TP_P3, MDI_TN_P3, MDI_RP_P3, MDI_RN_P3,296 MDI_RP_P4, MDI_RN_P4, MDI_TP_P4, MDI_TN_P4, PMIC_SCL,297 PMIC_SDA, SPIC1_CLK, SPIC1_MOSI, SPIC1_MISO, SPIC1_CS,298 GPIO_D, WATCHDOG, RTS3_N, CTS3_N, TXD3, RXD3, PERST0_N,299 PERST1_N, WLED_N, EPHY_LED0_N, AUXIN0, AUXIN1, AUXIN2,300 AUXIN3, TXD4, RXD4, RTS4_N, CST4_N, PWM1, PWM2, PWM3, PWM4,301 PWM5, PWM6, PWM7, GPIO_E, TOP_5G_CLK, TOP_5G_DATA,302 WF0_5G_HB0, WF0_5G_HB1, WF0_5G_HB2, WF0_5G_HB3, WF0_5G_HB4,303 WF0_5G_HB5, WF0_5G_HB6, XO_REQ, TOP_RST_N, SYS_WATCHDOG,304 EPHY_LED0_N_JTDO, EPHY_LED1_N_JTDI, EPHY_LED2_N_JTMS,305 EPHY_LED3_N_JTCLK, EPHY_LED4_N_JTRST_N, WF2G_LED_N,306 WF5G_LED_N, GPIO_9, GPIO_10, GPIO_11, GPIO_12, UART1_TXD,307 UART1_RXD, UART1_CTS, UART1_RTS, UART2_TXD, UART2_RXD,308 UART2_CTS, UART2_RTS, SMI_MDC, SMI_MDIO, PCIE_PERESET_N,309 PWM_0, GPIO_0, GPIO_1, GPIO_2, GPIO_3, GPIO_4, GPIO_5,310 GPIO_6, GPIO_7, GPIO_8, UART0_TXD, UART0_RXD, TOP_2G_CLK,311 TOP_2G_DATA, WF0_2G_HB0, WF0_2G_HB1, WF0_2G_HB2, WF0_2G_HB3,312 WF0_2G_HB4, WF0_2G_HB5, WF0_2G_HB6]313 314 bias-disable: true315 316 bias-pull-up: true317 318 bias-pull-down: true319 320 input-enable: true321 322 input-disable: true323 324 output-enable: true325 326 output-low: true327 328 output-high: true329 330 input-schmitt-enable: true331 332 input-schmitt-disable: true333 334 drive-strength:335 enum: [4, 8, 12, 16]336 337 slew-rate:338 enum: [0, 1]339 340 mediatek,tdsel:341 description:342 An integer describing the steps for output level shifter duty343 cycle when asserted (high pulse width adjustment). Valid arguments344 are from 0 to 15.345 $ref: /schemas/types.yaml#/definitions/uint32346 347 mediatek,rdsel:348 description:349 An integer describing the steps for input level shifter duty cycle350 when asserted (high pulse width adjustment). Valid arguments are351 from 0 to 63.352 $ref: /schemas/types.yaml#/definitions/uint32353 354 required:355 - pins356 357additionalProperties: false358 359examples:360 - |361 #include <dt-bindings/interrupt-controller/irq.h>362 #include <dt-bindings/interrupt-controller/arm-gic.h>363 364 soc {365 #address-cells = <2>;366 #size-cells = <2>;367 368 pio: pinctrl@10211000 {369 compatible = "mediatek,mt7622-pinctrl";370 reg = <0 0x10211000 0 0x1000>;371 gpio-controller;372 #gpio-cells = <2>;373 374 pinctrl_eth_default: eth-pins {375 mux-mdio {376 groups = "mdc_mdio";377 function = "eth";378 drive-strength = <12>;379 };380 381 mux-gmac2 {382 groups = "rgmii_via_gmac2";383 function = "eth";384 drive-strength = <12>;385 };386 387 mux-esw {388 groups = "esw";389 function = "eth";390 drive-strength = <8>;391 };392 393 conf-mdio {394 pins = "MDC";395 bias-pull-up;396 };397 };398 };399 };400