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1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)2%YAML 1.23---4$id: http://devicetree.org/schemas/pinctrl/mediatek,mt8192-pinctrl.yaml#5$schema: http://devicetree.org/meta-schemas/core.yaml#6 7title: MediaTek MT8192 Pin Controller8 9maintainers:10 - Sean Wang <sean.wang@mediatek.com>11 12description:13 The MediaTek's MT8192 Pin controller is used to control SoC pins.14 15properties:16 compatible:17 const: mediatek,mt8192-pinctrl18 19 gpio-controller: true20 21 '#gpio-cells':22 description:23 Number of cells in GPIO specifier. Since the generic GPIO binding is used,24 the amount of cells must be specified as 2. See the below mentioned gpio25 binding representation for description of particular cells.26 const: 227 28 gpio-ranges:29 description: GPIO valid number range.30 maxItems: 131 32 gpio-line-names: true33 34 reg:35 description:36 Physical address base for GPIO base registers. There are 11 GPIO physical37 address base in mt8192.38 maxItems: 1139 40 reg-names:41 description:42 GPIO base register names.43 maxItems: 1144 45 interrupt-controller: true46 47 '#interrupt-cells':48 const: 249 50 interrupts:51 description: The interrupt outputs to sysirq.52 maxItems: 153 54# PIN CONFIGURATION NODES55patternProperties:56 '-pins$':57 type: object58 additionalProperties: false59 patternProperties:60 '^pins':61 type: object62 description:63 A pinctrl node should contain at least one subnodes representing the64 pinctrl groups available on the machine. Each subnode will list the65 pins it needs, and how they should be configured, with regard to muxer66 configuration, pullups, drive strength, input enable/disable and input67 schmitt.68 $ref: pinmux-node.yaml69 70 properties:71 pinmux:72 description:73 Integer array, represents gpio pin number and mux setting.74 Supported pin number and mux varies for different SoCs, and are75 defined as macros in dt-bindings/pinctrl/<soc>-pinfunc.h directly.76 77 drive-strength:78 description:79 It can support some arguments, such as MTK_DRIVE_4mA,80 MTK_DRIVE_6mA, etc. See dt-bindings/pinctrl/mt65xx.h. It can only81 support 2/4/6/8/10/12/14/16mA in mt8192.82 enum: [2, 4, 6, 8, 10, 12, 14, 16]83 84 drive-strength-microamp:85 enum: [125, 250, 500, 1000]86 87 bias-pull-down:88 oneOf:89 - type: boolean90 description: normal pull down.91 - enum: [100, 101, 102, 103]92 description: PUPD/R1/R0 pull down type. See MTK_PUPD_SET_R1R0_93 defines in dt-bindings/pinctrl/mt65xx.h.94 - enum: [200, 201, 202, 203]95 description: RSEL pull down type. See MTK_PULL_SET_RSEL_ defines96 in dt-bindings/pinctrl/mt65xx.h.97 98 bias-pull-up:99 oneOf:100 - type: boolean101 description: normal pull up.102 - enum: [100, 101, 102, 103]103 description: PUPD/R1/R0 pull up type. See MTK_PUPD_SET_R1R0_104 defines in dt-bindings/pinctrl/mt65xx.h.105 - enum: [200, 201, 202, 203]106 description: RSEL pull up type. See MTK_PULL_SET_RSEL_ defines107 in dt-bindings/pinctrl/mt65xx.h.108 109 bias-disable: true110 111 output-high: true112 113 output-low: true114 115 input-enable: true116 117 input-disable: true118 119 input-schmitt-enable: true120 121 input-schmitt-disable: true122 123 required:124 - pinmux125 126 additionalProperties: false127 128allOf:129 - $ref: pinctrl.yaml#130 131required:132 - compatible133 - reg134 - interrupts135 - interrupt-controller136 - '#interrupt-cells'137 - gpio-controller138 - '#gpio-cells'139 - gpio-ranges140 141additionalProperties: false142 143examples:144 - |145 #include <dt-bindings/pinctrl/mt8192-pinfunc.h>146 #include <dt-bindings/interrupt-controller/arm-gic.h>147 pio: pinctrl@10005000 {148 compatible = "mediatek,mt8192-pinctrl";149 reg = <0x10005000 0x1000>,150 <0x11c20000 0x1000>,151 <0x11d10000 0x1000>,152 <0x11d30000 0x1000>,153 <0x11d40000 0x1000>,154 <0x11e20000 0x1000>,155 <0x11e70000 0x1000>,156 <0x11ea0000 0x1000>,157 <0x11f20000 0x1000>,158 <0x11f30000 0x1000>,159 <0x1000b000 0x1000>;160 reg-names = "iocfg0", "iocfg_rm", "iocfg_bm",161 "iocfg_bl", "iocfg_br", "iocfg_lm",162 "iocfg_lb", "iocfg_rt", "iocfg_lt",163 "iocfg_tl", "eint";164 gpio-controller;165 #gpio-cells = <2>;166 gpio-ranges = <&pio 0 0 220>;167 interrupt-controller;168 interrupts = <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH 0>;169 #interrupt-cells = <2>;170 171 spi1-default-pins {172 pins-cs-mosi-clk {173 pinmux = <PINMUX_GPIO157__FUNC_SPI1_A_CSB>,174 <PINMUX_GPIO159__FUNC_SPI1_A_MO>,175 <PINMUX_GPIO156__FUNC_SPI1_A_CLK>;176 bias-disable;177 };178 179 pins-miso {180 pinmux = <PINMUX_GPIO158__FUNC_SPI1_A_MI>;181 bias-pull-down;182 };183 };184 };185