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1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)2%YAML 1.23---4$id: http://devicetree.org/schemas/pinctrl/mediatek,mt8365-pinctrl.yaml#5$schema: http://devicetree.org/meta-schemas/core.yaml#6 7title: MediaTek MT8365 Pin Controller8 9maintainers:10 - Zhiyong Tao <zhiyong.tao@mediatek.com>11 - Bernhard Rosenkränzer <bero@baylibre.com>12 13description:14 The MediaTek's MT8365 Pin controller is used to control SoC pins.15 16properties:17 compatible:18 const: mediatek,mt8365-pinctrl19 20 reg:21 maxItems: 122 23 mediatek,pctl-regmap:24 $ref: /schemas/types.yaml#/definitions/phandle-array25 items:26 maxItems: 127 minItems: 128 maxItems: 229 description:30 Should be phandles of the syscfg node.31 32 gpio-controller: true33 34 "#gpio-cells":35 const: 236 description:37 Number of cells in GPIO specifier. Since the generic GPIO binding is used,38 the amount of cells must be specified as 2. See the below mentioned gpio39 binding representation for description of particular cells.40 41 interrupt-controller: true42 43 interrupts:44 maxItems: 145 46 "#interrupt-cells":47 const: 248 49patternProperties:50 "-pins$":51 type: object52 additionalProperties: false53 patternProperties:54 "pins$":55 type: object56 additionalProperties: false57 description:58 A pinctrl node should contain at least one subnode representing the59 pinctrl groups available on the machine. Each subnode will list the60 pins it needs, and how they should be configured, with regard to muxer61 configuration, pullups, drive strength, input enable/disable and input62 schmitt.63 $ref: /schemas/pinctrl/pincfg-node.yaml64 65 properties:66 pinmux:67 description:68 Integer array, represents gpio pin number and mux setting.69 Supported pin number and mux varies for different SoCs, and are70 defined as macros in <soc>-pinfunc.h directly.71 72 bias-disable: true73 74 bias-pull-up:75 oneOf:76 - type: boolean77 - enum: [100, 101, 102, 103]78 description: Pull up R1/R0 type define value.79 description: |80 For pull up type is normal, it don't need add R1/R0 define.81 For pull up type is R1/R0 type, it can add value to set different82 resistance. Valid arguments are described as below:83 100: (R1, R0) = (0, 0) which means R1 disabled and R0 disabled.84 101: (R1, R0) = (0, 1) which means R1 disabled and R0 enabled.85 102: (R1, R0) = (1, 0) which means R1 enabled and R0 disabled.86 103: (R1, R0) = (1, 1) which means R1 enabled and R0 enabled.87 88 bias-pull-down:89 oneOf:90 - type: boolean91 - enum: [100, 101, 102, 103]92 description: Pull down R1/R0 type define value.93 description: |94 For pull down type is normal, it don't need add R1/R0 define.95 For pull down type is R1/R0 type, it can add value to set96 different resistance. Valid arguments are described as below:97 100: (R1, R0) = (0, 0) which means R1 disabled and R0 disabled.98 101: (R1, R0) = (0, 1) which means R1 disabled and R0 enabled.99 102: (R1, R0) = (1, 0) which means R1 enabled and R0 disabled.100 103: (R1, R0) = (1, 1) which means R1 enabled and R0 enabled.101 102 drive-strength:103 enum: [2, 4, 6, 8, 10, 12, 14, 16]104 105 input-enable: true106 107 input-disable: true108 109 output-low: true110 111 output-high: true112 113 input-schmitt-enable: true114 115 input-schmitt-disable: true116 117 drive-strength-microamp:118 enum: [125, 250, 500, 1000]119 120 mediatek,drive-strength-adv:121 deprecated: true122 description: |123 DEPRECATED: Please use drive-strength-microamp instead.124 Describe the specific driving setup property.125 For I2C pins, the existing generic driving setup can only support126 2/4/6/8/10/12/14/16mA driving. But in specific driving setup, they127 can support 0.125/0.25/0.5/1mA adjustment. If we enable specific128 driving setup, the existing generic setup will be disabled.129 The specific driving setup is controlled by E1E0EN.130 When E1=0/E0=0, the strength is 0.125mA.131 When E1=0/E0=1, the strength is 0.25mA.132 When E1=1/E0=0, the strength is 0.5mA.133 When E1=1/E0=1, the strength is 1mA.134 EN is used to enable or disable the specific driving setup.135 Valid arguments are described as below:136 0: (E1, E0, EN) = (0, 0, 0)137 1: (E1, E0, EN) = (0, 0, 1)138 2: (E1, E0, EN) = (0, 1, 0)139 3: (E1, E0, EN) = (0, 1, 1)140 4: (E1, E0, EN) = (1, 0, 0)141 5: (E1, E0, EN) = (1, 0, 1)142 6: (E1, E0, EN) = (1, 1, 0)143 7: (E1, E0, EN) = (1, 1, 1)144 So the valid arguments are from 0 to 7.145 $ref: /schemas/types.yaml#/definitions/uint32146 enum: [0, 1, 2, 3, 4, 5, 6, 7]147 148 mediatek,pull-up-adv:149 deprecated: true150 description: |151 DEPRECATED: Please use bias-pull-up instead.152 Pull up settings for 2 pull resistors, R0 and R1. User can153 configure those special pins. Valid arguments are described as154 below:155 0: (R1, R0) = (0, 0) which means R1 disabled and R0 disabled.156 1: (R1, R0) = (0, 1) which means R1 disabled and R0 enabled.157 2: (R1, R0) = (1, 0) which means R1 enabled and R0 disabled.158 3: (R1, R0) = (1, 1) which means R1 enabled and R0 enabled.159 $ref: /schemas/types.yaml#/definitions/uint32160 enum: [0, 1, 2, 3]161 162 mediatek,pull-down-adv:163 deprecated: true164 description: |165 DEPRECATED: Please use bias-pull-down instead.166 Pull down settings for 2 pull resistors, R0 and R1. User can167 configure those special pins. Valid arguments are described as168 below:169 0: (R1, R0) = (0, 0) which means R1 disabled and R0 disabled.170 1: (R1, R0) = (0, 1) which means R1 disabled and R0 enabled.171 2: (R1, R0) = (1, 0) which means R1 enabled and R0 disabled.172 3: (R1, R0) = (1, 1) which means R1 enabled and R0 enabled.173 $ref: /schemas/types.yaml#/definitions/uint32174 enum: [0, 1, 2, 3]175 176 mediatek,tdsel:177 description:178 An integer describing the steps for output level shifter duty179 cycle when asserted (high pulse width adjustment). Valid arguments180 are from 0 to 15.181 $ref: /schemas/types.yaml#/definitions/uint32182 183 mediatek,rdsel:184 description:185 An integer describing the steps for input level shifter duty cycle186 when asserted (high pulse width adjustment). Valid arguments are187 from 0 to 63.188 $ref: /schemas/types.yaml#/definitions/uint32189 190 required:191 - pinmux192 193required:194 - compatible195 - reg196 - gpio-controller197 - "#gpio-cells"198 199allOf:200 - $ref: pinctrl.yaml#201 202additionalProperties: false203 204examples:205 - |206 #include <dt-bindings/interrupt-controller/arm-gic.h>207 #include <dt-bindings/pinctrl/mt8365-pinfunc.h>208 soc {209 #address-cells = <2>;210 #size-cells = <2>;211 212 pio: pinctrl@1000b000 {213 compatible = "mediatek,mt8365-pinctrl";214 reg = <0 0x1000b000 0 0x1000>;215 mediatek,pctl-regmap = <&syscfg_pctl>;216 gpio-controller;217 #gpio-cells = <2>;218 interrupt-controller;219 #interrupt-cells = <2>;220 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;221 222 pio-pins {223 pins {224 pinmux = <MT8365_PIN_59_SDA1__FUNC_SDA1_0>, <MT8365_PIN_60_SCL1__FUNC_SCL1_0>;225 mediatek,pull-up-adv = <3>;226 bias-pull-up;227 };228 };229 };230 };231