163 lines · yaml
1# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause2%YAML 1.23---4$id: http://devicetree.org/schemas/pinctrl/nuvoton,wpcm450-pinctrl.yaml#5$schema: http://devicetree.org/meta-schemas/core.yaml#6 7title: Nuvoton WPCM450 pin control and GPIO8 9maintainers:10 - Jonathan Neuschäfer <j.neuschaefer@gmx.net>11 12properties:13 compatible:14 const: nuvoton,wpcm450-pinctrl15 16 reg:17 maxItems: 118 19 '#address-cells':20 const: 121 22 '#size-cells':23 const: 024 25patternProperties:26 # There are three kinds of subnodes:27 # 1. a GPIO controller node for each GPIO bank28 # 2. a pinmux node configures pin muxing for a group of pins (e.g. rmii2)29 # 3. a pinconf node configures properties of a single pin30 31 "^gpio@[0-7]$":32 type: object33 additionalProperties: false34 35 description:36 Eight GPIO banks (gpio@0 to gpio@7), that each contain between 14 and 1837 GPIOs. Some GPIOs support interrupts.38 39 properties:40 reg:41 minimum: 042 maximum: 743 44 gpio-controller: true45 46 "#gpio-cells":47 const: 248 49 interrupt-controller: true50 51 "#interrupt-cells":52 const: 253 54 interrupts:55 maxItems: 356 description:57 The interrupts associated with this GPIO bank58 59 required:60 - reg61 - gpio-controller62 - '#gpio-cells'63 64 "^mux-":65 $ref: pinmux-node.yaml#66 67 properties:68 groups:69 description:70 One or more groups of pins to mux to a certain function71 items:72 enum: [ smb3, smb4, smb5, scs1, scs2, scs3, smb0, smb1, smb2, bsp,73 hsp1, hsp2, r1err, r1md, rmii2, r2err, r2md, kbcc, dvo,74 clko, smi, uinc, gspi, mben, xcs2, xcs1, sdio, sspi, fi0,75 fi1, fi2, fi3, fi4, fi5, fi6, fi7, fi8, fi9, fi10, fi11,76 fi12, fi13, fi14, fi15, pwm0, pwm1, pwm2, pwm3, pwm4, pwm5,77 pwm6, pwm7, hg0, hg1, hg2, hg3, hg4, hg5, hg6, hg7 ]78 function:79 description:80 The function that a group of pins is muxed to81 enum: [ smb3, smb4, smb5, scs1, scs2, scs3, smb0, smb1, smb2, bsp,82 hsp1, hsp2, r1err, r1md, rmii2, r2err, r2md, kbcc, dvo0,83 dvo1, dvo2, dvo3, dvo4, dvo5, dvo6, dvo7, clko, smi, uinc,84 gspi, mben, xcs2, xcs1, sdio, sspi, fi0, fi1, fi2, fi3, fi4,85 fi5, fi6, fi7, fi8, fi9, fi10, fi11, fi12, fi13, fi14, fi15,86 pwm0, pwm1, pwm2, pwm3, pwm4, pwm5, pwm6, pwm7, hg0, hg1,87 hg2, hg3, hg4, hg5, hg6, hg7, gpio ]88 89 dependencies:90 groups: [ function ]91 function: [ groups ]92 93 additionalProperties: false94 95 "^cfg-":96 $ref: pincfg-node.yaml#97 98 properties:99 pins:100 description:101 A list of pins to configure in certain ways, such as enabling102 debouncing103 items:104 pattern: "^gpio1?[0-9]{1,2}$"105 106 input-debounce:107 maxItems: 1108 109 additionalProperties: false110 111required:112 - compatible113 - reg114 115additionalProperties: false116 117examples:118 - |119 #include <dt-bindings/interrupt-controller/irq.h>120 #include <dt-bindings/gpio/gpio.h>121 pinctrl: pinctrl@b8003000 {122 compatible = "nuvoton,wpcm450-pinctrl";123 reg = <0xb8003000 0x1000>;124 #address-cells = <1>;125 #size-cells = <0>;126 127 gpio0: gpio@0 {128 reg = <0>;129 gpio-controller;130 #gpio-cells = <2>;131 interrupts = <2 IRQ_TYPE_LEVEL_HIGH>,132 <3 IRQ_TYPE_LEVEL_HIGH>,133 <4 IRQ_TYPE_LEVEL_HIGH>;134 };135 136 mux-rmii2 {137 groups = "rmii2";138 function = "rmii2";139 };140 141 pinmux_uid: mux-uid {142 groups = "gspi", "sspi";143 function = "gpio";144 };145 146 pinctrl_uid: cfg-uid {147 pins = "gpio14";148 input-debounce = <1>;149 };150 };151 152 gpio-keys {153 compatible = "gpio-keys";154 pinctrl-names = "default";155 pinctrl-0 = <&pinctrl_uid>, <&pinmux_uid>;156 157 button-uid {158 label = "UID";159 linux,code = <102>;160 gpios = <&gpio0 14 GPIO_ACTIVE_HIGH>;161 };162 };163