216 lines · yaml
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)2%YAML 1.23---4$id: http://devicetree.org/schemas/pinctrl/pinctrl-single.yaml#5$schema: http://devicetree.org/meta-schemas/core.yaml#6 7title: Generic Pin Controller with a Single Register for One or More Pins8 9maintainers:10 - Tony Lindgren <tony@atomide.com>11 12description:13 Some pin controller devices use a single register for one or more pins. The14 range of pin control registers can vary from one to many for each controller15 instance. Some SoCs from Altera, Broadcom, HiSilicon, Ralink, and TI have this16 kind of pin controller instances.17 18properties:19 compatible:20 oneOf:21 - enum:22 - pinctrl-single23 - pinconf-single24 - items:25 - enum:26 - ti,am437-padconf27 - ti,am654-padconf28 - ti,dra7-padconf29 - ti,omap2420-padconf30 - ti,omap2430-padconf31 - ti,omap3-padconf32 - ti,omap4-padconf33 - ti,omap5-padconf34 - ti,j7200-padconf35 - const: pinctrl-single36 37 reg:38 maxItems: 139 40 interrupt-controller: true41 42 '#interrupt-cells':43 const: 144 45 '#address-cells':46 const: 147 48 '#size-cells':49 const: 050 51 '#pinctrl-cells':52 description:53 Number of cells. Usually 2, consisting of register offset, pin configuration54 value, and pinmux mode. Some controllers may use 1 for just offset and value.55 enum: [ 1, 2 ]56 57 pinctrl-single,bit-per-mux:58 description: Optional flag to indicate register controls more than one pin59 type: boolean60 61 pinctrl-single,function-mask:62 description: Mask of the allowed register bits63 $ref: /schemas/types.yaml#/definitions/uint3264 65 pinctrl-single,function-off:66 description: Optional function off mode for disabled state67 $ref: /schemas/types.yaml#/definitions/uint3268 69 pinctrl-single,register-width:70 description: Width of pin specific bits in the register71 $ref: /schemas/types.yaml#/definitions/uint3272 enum: [ 8, 16, 32 ]73 74 pinctrl-single,gpio-range:75 description: Optional list of pin base, nr pins & gpio function76 $ref: /schemas/types.yaml#/definitions/phandle-array77 items:78 items:79 - description: phandle of a gpio-range node80 - description: pin base81 - description: number of pins82 - description: gpio function83 84 '#gpio-range-cells':85 description: No longer needed, may exist in older files for gpio-ranges86 deprecated: true87 const: 388 89 gpio-range:90 description: Optional node for gpio range cells91 type: object92 additionalProperties: false93 properties:94 '#pinctrl-single,gpio-range-cells':95 description: Number of gpio range cells96 const: 397 $ref: /schemas/types.yaml#/definitions/uint3298 99patternProperties:100 '-pins(-[0-9]+)?$|-pin$':101 description:102 Pin group node name using naming ending in -pins followed by an optional103 instance number104 type: object105 additionalProperties: false106 107 properties:108 pinctrl-single,pins:109 description:110 Array of pins as described in pinmux-node.yaml for pinctrl-pin-array111 $ref: /schemas/types.yaml#/definitions/uint32-array112 113 pinctrl-single,bits:114 description: Register bit configuration for pinctrl-single,bit-per-mux115 $ref: /schemas/types.yaml#/definitions/uint32-array116 items:117 - description: register offset118 - description: value119 - description: pin bitmask in the register120 121 pinctrl-single,bias-pullup:122 description: Optional bias pull up configuration123 $ref: /schemas/types.yaml#/definitions/uint32-array124 items:125 - description: input126 - description: enabled pull up bits127 - description: disabled pull up bits128 - description: bias pull up mask129 130 pinctrl-single,bias-pulldown:131 description: Optional bias pull down configuration132 $ref: /schemas/types.yaml#/definitions/uint32-array133 items:134 - description: input135 - description: enabled pull down bits136 - description: disabled pull down bits137 - description: bias pull down mask138 139 pinctrl-single,drive-strength:140 description: Optional drive strength configuration141 $ref: /schemas/types.yaml#/definitions/uint32-array142 items:143 - description: drive strength current144 - description: drive strength mask145 146 pinctrl-single,input-schmitt:147 description: Optional schmitt strength configuration148 $ref: /schemas/types.yaml#/definitions/uint32-array149 items:150 - description: schmitt strength current151 - description: schmitt strength mask152 153 pinctrl-single,input-schmitt-enable:154 description: Optional input schmitt configuration155 $ref: /schemas/types.yaml#/definitions/uint32-array156 items:157 - description: input158 - description: enable bits159 - description: disable bits160 - description: input schmitt mask161 162 pinctrl-single,low-power-mode:163 description: Optional low power mode configuration164 $ref: /schemas/types.yaml#/definitions/uint32-array165 items:166 - description: low power mode value167 - description: low power mode mask168 169 pinctrl-single,slew-rate:170 description: Optional slew rate configuration171 $ref: /schemas/types.yaml#/definitions/uint32-array172 items:173 - description: slew rate174 - description: slew rate mask175 176allOf:177 - $ref: pinctrl.yaml#178 179required:180 - compatible181 - reg182 - pinctrl-single,register-width183 184additionalProperties: false185 186examples:187 - |188 soc {189 #address-cells = <1>;190 #size-cells = <1>;191 192 pinmux@4a100040 {193 compatible = "pinctrl-single";194 reg = <0x4a100040 0x0196>;195 #address-cells = <1>;196 #size-cells = <0>;197 #pinctrl-cells = <2>;198 #interrupt-cells = <1>;199 interrupt-controller;200 pinctrl-single,register-width = <16>;201 pinctrl-single,function-mask = <0xffff>;202 pinctrl-single,gpio-range = <&range 0 3 0>;203 range: gpio-range {204 #pinctrl-single,gpio-range-cells = <3>;205 };206 207 uart2-pins {208 pinctrl-single,pins =209 <0xd8 0x118>,210 <0xda 0>,211 <0xdc 0x118>,212 <0xde 0>;213 };214 };215 };216